Pixel structure, display panel and manufacturing method of pixel structure

1. A pixel structure, comprising:

a plurality of gate lines extending in parallel in a first direction;

a plurality of data lines extending in parallel in a second direction; and

a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines, wherein,

one of the data lines is disposed between each two pixel units which are adjacent to each other in the first direction, and two of the gate lines are disposed between each two pixel units which are adjacent to each other in the second direction; wherein,

each of the pixel units comprises two pixel regions which are arranged side by side in the first direction, each of the pixel regions comprises a pixel electrode, and each of the pixel units comprises a unitary common electrode which covers the two pixel regions; and wherein,

each of the pixel units comprises a first common electrode line extending in the first direction and a second common electrode line extending in the second direction, the common electrode is positioned in a common electrode layer, and the first common electrode line and the second common electrode line are electrically connected with the common electrode, respectively.

2. The pixel structure according to claim 1 , wherein,

the first common electrode line and the second common electrode line are electrically connected with each other at their intersection point; and wherein,

the first common electrode lines of the pixel units which are adjacent to each other in the first direction are electrically connected with each other, and the second common electrode lines of the pixel units which are adjacent to each other in the second direction are electrically connected with each other.

3. The pixel structure according to claim 2 , further comprising a first metal layer, a pixel electrode layer and an insulation layer between the first metal layer and the pixel electrode layer, wherein,

the first common electrode line, the second common electrode line and the gate line are positioned in the first metal layer,

the pixel electrode is positioned in the pixel electrode layer,

the first common electrode lines of the pixel units which are adjacent to each other in the first direction extend continuously in the first metal layer, so as to be electrically connected with each other, and

the second common electrode lines of the pixel units which are adjacent to each other in the second direction are broken off by the gate lines, the second common electrode lines of the pixel units which are adjacent to each other in the second direction are electrically connected with each other through a via-hole in the insulation layer and a connecting line in the pixel electrode layer, and the connecting line spans the gate lines between the two pixel units which are adjacent to each other in the second direction.

4. The pixel structure according to claim 3 , wherein the connecting line is formed from the same material as the pixel electrode.

5. The pixel structure according to claim 3 , wherein,

each of the pixel regions comprises a thin film transistor,

a gate electrode of each thin film transistor is electrically connected with a gate line, a source electrode of each thin film transistor is electrically connected with a data line, and a drain electrode of each thin film transistor is electrically connected with a pixel electrode of the pixel region where the thin film transistor is located through a via-hole, and

the gate electrodes of the respective thin film transistors in the two pixel regions of each pixel unit are electrically connected with the gate lines at two sides of the pixel unit, respectively.

6. The pixel structure according to claim 5 , wherein,

the respective thin film transistors in the two pixel regions of each pixel unit are diagonally arranged at two corners of the pixel unit.

7. The pixel structure according to claim 5 , further comprising a second metal layer formed between the first metal layer and the pixel electrode layer, wherein the data line, the source electrode and the drain electrode of the thin film transistor are positioned in the second metal layer.

8. The pixel structure according to claim 7 , wherein an insulation layer is provided between the first metal layer and the second metal layer, and between the second metal layer and the pixel electrode layer, respectively.

9. The pixel structure according to claim 3 , wherein the first common electrode line, the second common electrode and the gate line are formed from the same material.

10. The pixel structure according to claim 2 , wherein,

the first common electrode line is arranged in the first direction at an edge of each of the pixel units, and the second common electrode line is arranged in the second direction at a boundary between two pixel regions.

11. The pixel structure according to claim 2 , wherein the first common electrode lines of the respective pixel units are aligned with each other, and the second common electrode lines of the respective pixel units are aligned with each other.

12. A display panel comprising the pixel structure according to claim 1 .

13. A manufacturing method of a pixel structure, comprising:

providing a substrate;

forming a common electrode layer on the substrate, and patterning the common electrode layer to form a common electrode;

forming a first metal layer on the common electrode layer, and patterning the first metal layer to form a plurality of gate lines extending in parallel in a first direction, a plurality of first common electrode lines extending in the first direction and a plurality of second common electrode lines extending in a second direction, wherein the first common electrode lines and the second common electrode lines are electrically connected with each other at their intersection points;

forming a first insulation layer on the first metal layer;

forming a second metal layer on the first insulation layer, and patterning the second metal layer to form a plurality of data lines extending in parallel in the second direction;

forming a second insulation layer on the second metal layer; and

forming a transparent pixel electrode layer on the second insulation layer, and patterning the pixel electrode layer to form a pixel electrode; wherein,

the plurality of gate lines and the plurality of data lines define a plurality of pixel units,

one of the data lines is disposed between each two pixel units which are adjacent to each other in the first direction, and two of the gate lines are disposed between each two pixel units which are adjacent to each other in the second direction; wherein,

each of the pixel units comprises two pixel regions which are arranged side by side in the first direction, each of the pixel regions comprises a pixel electrode, and each of the pixel units comprises a unitary common electrode which covers the two pixel regions; and wherein,

the first common electrode line and the second common electrode line are formed such that the first common electrode line and the second common electrode line contact electrically with the common electrode, respectively.

14. The manufacturing method according to claim 13 , wherein,

each of the pixel units comprises a corresponding first common electrode line and a corresponding second common electrode line; and wherein,

the first common electrode lines of the pixel units which are adjacent to each other in the first direction are electrically connected with each other, and the second common electrode lines of the pixel units which are adjacent to each other in the second direction are electrically connected with each other.

15. The manufacturing method according to claim 14 , further comprising: forming a source electrode and a drain electrode of a thin film transistor while patterning the second metal layer to form the data line.

16. The manufacturing method according to claim 15 , further comprising:

patterning the second insulation layer to form a first via-hole which penetrates the first insulation layer and the second insulation layer and a second via-hole which penetrates the second insulation layer to connect the drain electrode of the thin film transistor with the pixel electrode.

17. The manufacturing method according to claim 16 , further comprising: forming a connecting line while patterning the pixel electrode layer to form the pixel electrode,

wherein the connecting line spans the gate lines between the pixel units which are adjacent to each other in the second direction.

18. The manufacturing method according to claim 17 , wherein,

the first common electrode lines of the pixel units which are adjacent to each other in the first direction extend continuously in the first metal layer, so as to be electrically connected with each other, and

the second common electrode lines of the pixel units which are adjacent to each other in the second direction are broken off by the gate lines, and are electrically connected with each other through the first via-hole which penetrates the first insulation layer and the second insulation layer and the connecting line in the pixel electrode layer.