Nanosheet CMOS transistors

1. A method of forming semiconductor devices, comprising:

forming a respective stack of sheets in two regions, each stack comprising first layers and second layers;

etching away the second layers in the first region;

annealing the second region to change the composition of the first layers in the second region by interaction with the second layers in the second region; and

forming a gate stack in the first and second region.

2. The method of claim 1 , wherein each stack further comprises third layers formed, wherein the first, second, and third layers are formed with a pattern CBABCBABC . . . , where A, B, and C represent the first, second, and third layers, respectively.

3. The method of claim 2 , further comprising recessing the second and third layers relative to the first layers.

4. The method of claim 3 , further comprising forming dielectric spacers on sidewalls of the second and third layers.

5. The method of claim 4 , further comprising growing source and drain regions from exposed sidewalls of the first layers.

6. The method of claim 2 , further comprising selectively etching away the third layers before etching away the second layers in the first region.

7. The method of claim 2 , wherein the first layers consist of silicon, the second layers comprise silicon germanium at a first germanium concentration, and the third layers comprise silicon germanium at a second, higher germanium concentration.

8. The method of claim 7 , wherein the first layers and the third layers have a thickness between about 5 nm and about 20 nm and wherein the second layers have a thickness between about 2 nm and about 6 nm.

9. The method of claim 8 , wherein the first layers and the third layers have a thickness between about 10 nm and about 12 nm and wherein the second layers have a thickness between about 3 nm and about 5 nm.

10. The method of claim 1 , further comprising etching away an oxide layer that remains on surfaces of the first layers after annealing.

11. A method of forming semiconductor devices, comprising:

forming a respective stack of sheets in two regions, each stack comprising first layers, second layers, and third layers, wherein the first layers consist of silicon the second layers comprise silicon germanium at a first concentration, and the third layers comprise silicon germanium at a second, higher concentration;

recessing the second and third layers relative to the first layers;

forming dielectric spacers on sidewalls of the second and third layers;

growing source and drain regions from exposed sidewalls of the first layers;

etching away the second layers in the first region;

annealing the second region to change the composition of the first layers in the second region by interaction with the second layers in the second region;

etching away an oxide layer that remains on surfaces of the first layers after annealing; and

forming a gate stack in the first and second region.

12. The method of claim 11 , wherein the first, second, and third layers are formed with a pattern CBABCBABC . . . , where A, B, and C represent the first, second, and third layers, respectively.

13. The method of claim 11 , further comprising selectively etching away the third layers before etching away the second layers in the first region.

14. The method of claim 11 , wherein the first layers and the third layers have a thickness between about 5 nm and about 20 nm and wherein the second layers have a thickness between about 2 nm and about 6 nm.

15. The method of claim 14 , wherein the first layers and the third layers have a thickness between about 10 nm and about 12 nm and wherein the second layers have a thickness between about 3 nm and about 5 nm.