Strain gated transistors and method
A strain gated transistor and associated methods are shown. In one example, a transistor channel region includes a metal dichalcogen layer that is stressed to improve electrical properties of the transistor.
1. A semiconductor device, comprising:
a transition metal dichalcogenide layer formed on a substrate, the transition metal dichalcogenide layer comprising a channel region, the channel region coupled between a first source/drain region and a second source/drain region;
the first source/drain region and the second source/drain region penetrating within a thickness of the transition metal dichalcogenide layer;
a top gate located adjacent to the channel region and separated therefrom by a conformal gate dielectric formed over the first source/drain region, the second source/drain region, the channel region, and a portion of the substrate that is not covered by the first source/drain region, the second source/drain region and the channel region; and
a strain layer coupled adjacent to the channel region to provide a uniaxial tensile strain in the transition metal dichalcogenide channel region.
2. The semiconductor device of claim 1 , wherein the transition metal dichalcogenide channel region includes molybdenum disulfide.
3. The semiconductor device of claim 1 , wherein the transition metal dichalcogenide channel region includes a bilayer of transition metal dichalcogenide.
4. The semiconductor device of claim 1 , wherein the strain layer includes silicon nitride.
5. The semiconductor device of claim 1 , wherein the strain layer is coupled over the gate.
6. The semiconductor device of claim 1 , wherein the first source/drain region, and the second source/drain region are coupled to the transition metal dichalcogenide channel region as edge contacts.
7. The semiconductor device of claim 1 , wherein the conformal gate dielectric includes an aluminum oxide layer forming a direct interface with the transition metal dichalcogenide channel region.
8. The semiconductor device of claim 7 , wherein the conformal gate dielectric includes a hafnium oxide layer forming a direct interface with the aluminum oxide layer.
9. A method of forming a semiconductor device, comprising:
forming a transition metal dichalcogenide layer on a substrate;
removing a portion of the transition metal dichalcogenide layer to form a channel region;
forming a first source/drain region and a second source/drain region penetrating within a thickness of the transition metal dichalcogenide layer;
forming a conformal gate dielectric over the first source/drain region, the second source/drain region, the channel region, and a portion of the substrate that is not covered by the first source/drain region, the second source/drain region and the channel region;
forming a top gate on the conformal gate dielectric;
coupling a strain layer adjacent to the channel region to provide a uniaxial tensile strain in the channel region.
10. The method of claim 9 , wherein forming the transition metal dichalcogenide layer on the substrate includes exfoliating a layer of molybdenum disulfide and physically transferring the exfoliated layer of molybdenum disulfide to the substrate.
11. The method of claim 9 , wherein coupling the strain layer to the semiconductor device includes plasma enhanced chemical vapor deposition of a silicon nitride layer.
12. The method of claim 9 , wherein forming the first source/drain region, and the second source/drain region includes forming trenches in the transition metal dichalcogenide layer to expose edges and coupling the first source/drain region and the second source/drain region to the exposed edges.
13. The method of claim 12 , wherein forming trenches in the transition metal dichalcogenide layer includes plasma etching the transition metal dichalcogenide layer.