Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate.
1. A method of forming a first vertical field effect transistor (vFET), comprising:
forming a bottom source/drain (S/D) region disposed on a semiconductor substrate;
forming a fin disposed above said bottom S/D region;
forming a top source/drain (S/D) region disposed above said fin and having a top surface;
forming a gate layer laterally surrounding said fin;
patterning a mask over a first portion of said gate layer, wherein said first portion of said gate layer has a top surface above the top surface of the top S/D region;
surrounding at least partially said first portion of said gate layer and said mask on top thereof with an interlayer dielectric (ILD) layer;
removing at least a portion of said mask, thereby forming a gate contact opening directly over said first portion of said gate layer; and
filling said gate contact opening with a gate contact material.
2. The method of claim 1 , further comprising:
forming a spacer surrounding and over said top S/D region before forming said gate layer, said spacer being over a third portion of said gate layer adjacent to said fin, wherein said mask is deposited partially over said spacer.
3. The method of claim 2 , wherein surrounding at least partially said first portion of said gate layer and said mask on top thereof with said ILD layer comprises removing a second portion of said gate layer not covered by said mask and not covered by the spacer, to yield a space; and depositing said ILD layer in said space.
4. The method of claim 2 , further comprising forming a second vFET comprising a bottom source/drain (S/D) region disposed on a semiconductor substrate; a fin disposed above said bottom S/D region; a top source/drain (S/D) region disposed above said fin and having a top surface; a gate layer having a top surface higher than said top surface of said top S/D region; and a gate contact opening filled with a gate contact material over said gate; wherein said first vFET has a long axis parallel to a long axis of said second vFET.
5. The method of claim 4 , wherein a fin pitch between said first vFET and said second vFET is 36 nm or less.
6. The method of claim 1 , further comprising:
forming a top S/D contact opening in said ILD over said top S/D region;
forming a bottom S/D contact opening in said ILD over said bottom S/D region;
filling said top S/D contact opening with a top S/D contact material; and
filling said bottom S/D contact opening with a bottom S/D contact material.
7. The method of claim 1 , wherein said gate contact opening is aligned with said first portion of said gate layer.
8. A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device; and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;
wherein the semiconductor device processing system is adapted to:
form a bottom source/drain (S/D) region disposed on a semiconductor substrate;
form a fin disposed above said bottom S/D region;
form a top source/drain (S/D) region disposed above said fin and having a top surface;
form a gate layer laterally surrounding said fin;
pattern a mask over a first portion of said gate layer, wherein said first portion of said gate layer has a top surface above the top surface of the top S/D region;
surround at least partially said first portion of said gate layer and said mask on top thereof with an interlayer dielectric (ILD) layer;
remove at least a portion of said mask, thereby forming a gate contact opening directly over said first portion of said gate layer; and
fill said gate contact opening with a gate contact material.
9. The system of claim 8 , wherein said semiconductor device processing system is further adapted to:
form a spacer surrounding and over said top S/D region before forming said gate layer, said spacer being over a third portion of said gate layer adjacent to said fin, wherein said mask is deposited partially over said spacer.
10. The system of claim 9 , wherein said semiconductor device processing system is further adapted to:
form a top S/D contact opening in said ILD over said top S/D region;
form a bottom S/D contact opening in said ILD over said bottom S/D region;
fill said top S/D contact opening with a top S/D contact material; and
fill said bottom S/D contact opening with a bottom S/D contact material.