IP Library › Granted Patent US 10,263,617
Granted Patent B2
US 10,263,617 · App. 15/664,393 · Granted Apr 16, 2019

Semiconductor integrated circuit having a switch, an electrically-conductive electrode line and an electrically-conductive virtual line

Inventor: Hiromi Ogata (Kanagawa, JP)
Assignee: Sony Corporation
H03K17/6872H01L27/0207H01L27/092H03K3/012H03K17/16H03K19/0185H01L27/11807
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Quick Facts
Patent No.
US 10,263,617
App. No.
15/664,393
Granted
Apr 16, 2019
Kind
B2
Abstract

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Claims (27)

1. A semiconductor integrated circuit comprising:

a first control cell line in a first wiring layer, the first control cell line extends in parallel with a first direction;

a first branch line electrically connected to the first control cell line, the first branch line extends in parallel with a second direction;

a second control cell line in a second wiring layer, the second wiring layer is between a substrate and the first wiring layer; and

a contact that electrically connects the first control cell line to the second control cell line, the second control cell line extends in parallel with the first direction.

2. The semiconductor integrated circuit according to claim 1 , wherein the first control cell line is electrically connected directly to the first branch.

3. The semiconductor integrated circuit according to claim 1 , wherein the second control cell line is between the substrate and the first control cell line.

4. The semiconductor integrated circuit according to claim 1 , wherein the second direction differs from the first direction.

5. The semiconductor integrated circuit according to claim 1 , wherein the second direction is orthogonal to the first direction.

6. The semiconductor integrated circuit according to claim 1 , wherein the first branch line is between a source line and a drain line.

7. The semiconductor integrated circuit according to claim 6 , wherein the source line extends in parallel with the second direction.

8. The semiconductor integrated circuit according to claim 6 , wherein the drain line extends in parallel with the second direction.

9. The semiconductor integrated circuit according to claim 6 , wherein the source line is electrically connected to a source region of the substrate.

10. The semiconductor integrated circuit according to claim 9 , wherein the drain line is electrically connected to a drain region of the substrate.

11. The semiconductor integrated circuit according to claim 10 , wherein the source region and the drain region are of a same conductivity type.

12. The semiconductor integrated circuit according to claim 10 , wherein the source region and the drain region are N-type.

13. The semiconductor integrated circuit according to claim 10 , wherein the source region and the drain region are P-type.

14. The semiconductor integrated circuit according to claim 6 , wherein the source line is electrically connected to a voltage cell line.

15. The semiconductor integrated circuit according to claim 14 , wherein the voltage cell line extends in parallel with the first direction.

16. The semiconductor integrated circuit according to claim 14 , wherein the first branch line extends toward the voltage cell line and terminates before reaching the voltage cell line.

17. The semiconductor integrated circuit according to claim 14 , wherein the drain line extends toward the voltage cell line and terminates before reaching the voltage cell line.

18. The semiconductor integrated circuit according to claim 14 , wherein the voltage cell line comprises first lining wiring in the first wiring layer, the first lining wiring extends in parallel with the first direction.

19. The semiconductor integrated circuit according to claim 18 , wherein the voltage cell line comprises second lining wiring in the second wiring layer, the second lining wiring extends in parallel with the first direction.

20. The semiconductor integrated circuit according to claim 19 , wherein another contact electrically connects the first lining wiring to the second lining wiring.

21. The semiconductor integrated circuit according to claim 6 , wherein the drain line is between the first branch line and a second branch line.

22. The semiconductor integrated circuit according to claim 21 , wherein the second branch line extends in parallel with the second direction.

23. The semiconductor integrated circuit according to claim 21 , wherein the first control cell line is electrically connected to the second branch line.

Priority Claims (1)
JP 2007-241517 · Sep 18, 2007 · national
Continuity (7)
Continuation 14956250 · Dec 1, 2015
Continuation 14665662 · Mar 23, 2015
Continuation 14263598 · Apr 28, 2014
Continuation 13371994 · Feb 13, 2012
Continuation 12929180 · Jan 6, 2011
Continuation 12230098 · Aug 22, 2008
Related Publication 20170331472A1 · Nov 16, 2017