Apparatus and methods for tuning a voltage controlled oscillator
Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
1. An auto-tuning circuit for tuning a voltage controlled oscillator, comprising:
a prescaler circuit configured to receive a voltage controlled oscillator output signal from the voltage controlled oscillator and to generate a divided signal based on the voltage controlled oscillator output signal; and
a digital processing logic circuit configured to receive the divided signal and a reference clock signal, to count a number of cycles of the divided signal that occur during a calibration interval having a duration that is about equal to a first division ratio of the digital processing logic circuit divided by a frequency of the reference clock signal, and to cause the voltage controlled oscillator output signal to reach a coarse tuning target frequency in a coarse tuning mode based on the number of cycles.
2. The auto-tuning circuit of claim 1 wherein the digital processing logic circuit is further configured to determine a value of a capacitor array control signal based on the number of cycles of the divided signal.
3. The auto-tuning circuit of claim 1 wherein the digital processing logic circuit is further configured to determine a value of a capacitor array control signal to an initial value corresponding to an initial coarse tuning capacitance, the capacitor array control signal including a plurality of bits.
4. The auto-tuning circuit of claim 3 wherein the digital processing logic circuit is further configured to determine a final value of the capacitor array control signal based on comparing the number of cycles of the divided signal to a product of a second division ratio of a counter module and the first division ratio.
5. The auto-tuning circuit of claim 1 further comprising a counter module configured to generate, based on the divided signal, a feedback signal to be used for fine tuning the voltage controlled oscillator in a fine tuning mode.
6. The auto-tuning circuit of claim 5 wherein the digital processing logic circuit is further configured to generate a tuning control signal to configure a phase-locked loop between the fine tuning mode and the coarse tuning mode.
7. The auto-tuning circuit of claim 5 wherein the prescaler circuit further is configured to operate in both the fine tuning mode and the coarse tuning mode.
8. The auto-tuning circuit of claim 5 wherein the number of cycles counted is approximately equal to a product of a second division ratio of the counter module and the first division ratio.
9. The auto-tuning circuit of claim 1 wherein the prescaler circuit has a selectable division ratio, the auto-tuning circuit further comprising a counter module configured to control a value of the selectable division ratio to be one of a first integer division value P or a second integer division value P +1, the first integer division value P about equal to the first division ratio.
10. A phase-locked loop, comprising:
a capacitor array including a plurality capacitors digitally selectable by a capacitor array control signal;
a voltage controlled oscillator having a voltage input and configured to generate a voltage controlled oscillator output signal;
a prescaler circuit configured to receive the voltage controlled oscillator output signal and to generate a divided signal based on the voltage controlled oscillator output signal; and
a digital processing logic circuit configured to receive the divided signal and a reference clock signal, to count a number of cycles of the divided signal that occur during a calibration interval having a duration that is about equal to a first division ratio of the digital processing logic circuit divided by a frequency of the reference clock signal, and to cause the voltage controlled oscillator output signal to reach a coarse tuning target frequency in a coarse tuning mode based on the number of cycles.
11. The phase-locked loop of claim 10 wherein the digital processing logic circuit is further configured to determine a value of the capacitor array control signal based on the number of cycles of the divided signal.
12. The phase-locked loop of claim 10 wherein the voltage controlled oscillator is further configured to receive a reference voltage during the coarse tuning mode, the reference voltage proportional to temperature.
13. The phase-locked loop of claim 10 further comprising a counter module configured to generate, based on the divided signal, a feedback signal to be used for fine tuning the voltage controlled oscillator in a fine tuning mode.
14. The phase-locked loop of claim 13 wherein the digital processing logic circuit is further configured to generate a tuning control signal to configure the phase-locked loop between the fine tuning mode and the coarse tuning mode.
15. The phase-locked loop of claim 13 wherein the prescaler circuit further is configured to operate in both the fine tuning mode and the coarse tuning mode.
16. The phase-locked loop of claim 13 further comprising a phase-frequency detector and charge pump module configured to receive the feedback signal and the reference clock signal, the phase-frequency detector and charge pump module configured to generate a correction signal based on the feedback signal and the reference clock signal.
17. The phase-locked loop of claim 13 wherein the digital processing logic circuit is further configured to determine a value of the capacitor array control signal based on comparing the number of cycles of the divided signal to a product of a second division ratio of the counter module and the first division ratio.
18. A method of tuning a phase-locked loop, comprising:
generating a voltage controlled oscillator output signal using a voltage controlled oscillator coupled to a capacitor array including a plurality of capacitors digitally selectable by a capacitor array control signal;
dividing the voltage controlled oscillator output signal to generate a divided signal using a prescaler circuit;
counting a number of cycles of the divided signal that occur during a calibration interval having a duration that is about equal to a division ratio of a digital processing logic circuit divided by a frequency of a reference clock signal; and
causing the voltage controlled oscillator output signal to reach a coarse tuning target frequency in a coarse tuning mode based on the number of cycles.
19. The method of claim 18 further comprising generating, using a counter module based on the divided signal, a phase-frequency detector feedback signal to be used for fine tuning the voltage controlled oscillator in a fine tuning mode.
20. The method of claim 18 further comprising determining, using the digital processing logic circuit, a value of the capacitor array control signal based on the number of cycles of the divided signal.