Self-aligned EPI contact flow
Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.
1. A method, comprising:
removing a portion of each fin of a plurality of fins formed on a semiconductor substrate to expose a surface of a remaining portion of each fin, wherein the surface is recessed from a surface of a first dielectric material formed adjacent to each fin;
forming a feature on the surface of the remaining portion of each fin;
filling gaps between adjacent features with a second dielectric material; and
removing the features to form a plurality of openings in the second dielectric material, wherein the surface of the remaining portion of each fin is exposed.
2. The method of claim 1 , further comprising forming a fill material on the surface of the remaining portion of each fin, wherein each fill material is formed within a corresponding opening of the plurality of openings.
3. The method of claim 2 , wherein the fill material is formed in an epitaxial deposition chamber.
4. The method of claim 1 , wherein the features are formed in an epitaxial deposition chamber.
5. The method of claim 1 , wherein the features are removed by a selective etching process.
6. The method of claim 1 , wherein each feature is fabricated from a group III-V semiconductor material or a group II-VI semiconductor material.
7. The method of claim 1 , wherein each feature has a first width and each fin has a second width, wherein the first width is greater than the second width.
8. A method, comprising:
epitaxially forming a feature on each exposed portion of a plurality of exposed portions of a semiconductor surface, wherein the feature comprises a compound semiconductor material, wherein the exposed portions are separated by a first dielectric material disposed on covered portions of the semiconductor surface;
filling gaps between adjacent features with a second dielectric material;
removing the features to form a plurality of openings in the second dielectric material, wherein the exposed portions of the semiconductor surface are uncovered; and
depositing a fill material within each opening.
9. The method of claim 8 , further comprising performing a pre-clean process on the exposed portions of the semiconductor surface prior to forming the features.
10. The method of claim 8 , wherein the features are formed in an epitaxial deposition chamber.
11. The method of claim 8 , wherein the features are removed by a selective etching process.
12. The method of claim 8 , wherein the fill material is formed in an epitaxial deposition chamber.
13. The method of claim 8 , wherein the fill material comprises a semiconductive material or a conductive material.
14. A method, comprising:
removing semiconductor pillars to form a plurality of trenches in a dielectric material formed adjacent to the semiconductor pillars, wherein a semiconductor surface comprising a fin material is exposed in each trench;
forming a conductive source or drain material on each exposed semiconductor surface, wherein each source or drain material is formed within a corresponding trench of the plurality of trenches; and
forming a metal contact over each source or drain material, wherein the metal contact and a corresponding source or drain material are aligned within a corresponding trench of the plurality of trenches, and wherein a portion of each source or drain material proximate the metal contact has a rectangular cross-section.
15. The method of claim 14 , further comprising forming a silicide or germanide layer on each source or drain material prior to forming the metal contact over each source or drain material.
16. The method of claim 15 , further comprising forming a liner on the silicide or germanide layer prior to forming the metal contact over each source or drain material.
17. The method of claim 16 , wherein the metal contact is formed on the liner.
18. The method of claim 16 , wherein the metal contact comprises cobalt or tungsten.
19. The method of claim 14 , wherein the semiconductor pillars are removed by a selective etching process.
20. The method of claim 14 , wherein the source or drain material is formed in an epitaxial deposition chamber.