Methods, apparatus and system for replacement contact for a finFET device

1. A method, comprising:

forming a plurality of fins on a semiconductor substrate;

forming, over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion;

forming, over a second portion of the fins, a gate region;

performing a replacement metal gate (RMG) process in the gate region;

forming a trench in a portion of the gate region;

forming a void adjacent said a portion of said gate region;

forming a first silicon feature in said trench;

forming a second silicon feature in said void;

forming a TS cut region over said trench;

removing said first silicon feature and said second silicon feature; and

performing a metallization process in said void to form a contact.

2. The method of claim 1 , wherein performing a replacement metal gate (RMG) process in the gate region comprises:

performing a poly pull process for removing a poly gate material in a dummy gate area of said gate region;

depositing a work function metal (WFM) layer in a portion of place of said poly gate material;

depositing a gate metal over said WFM layer; and

forming a self-aligned cap (SAC) over said gate metal and said WFM layer.

3. The method of claim 1 , wherein forming a trench in a portion of the gate region comprises:

forming a cap over said SAC; and

removing a first oxide layer from said TS cut region.

4. The method of claim 3 , wherein forming said cap over said SAC comprises:

removing a portion of said SAC to form a recess in said SAC;

depositing a SOIC material into said recess in said SAC; and

performing a planarizing process on said SOIC material.

5. The method of claim 3 , wherein forming a void adjacent said a portion of said gate region comprises removing a second oxide layer from a region adjacent said cap and above said EPI feature.

6. The method of claim 1 , wherein:

forming said first silicon feature in said trench comprises depositing a silicon material into said trench and performing a chemical mechanical polishing process on said silicon material; and

forming said silicon feature in said trench comprises depositing a silicon material into said void and performing a chemical mechanical polishing process on said silicon material.

7. The method of claim 6 , wherein forming said TS cut region comprises:

depositing a thin oxide layer about said trench;

forming a nitride layer over said thin oxide layer; and

forming a oxide layer over said nitride layer.

8. The method of claim 7 , wherein removing said first silicon feature comprises:

performing a silicon etch process on said TS cut region;

depositing an oxide material into said TS cut region;

removing said low-k space, said ARC layer, and said PR layer; and

performing a silicon etch to remove silicon material from said void.

9. The method of claim 8 , wherein removing said second silicon feature comprises:

removing said thin oxide layer, said nitride layer, and said oxide layer; and

performing a silicon etch to remove silicon material from said void.

10. The method of claim 1 , wherein performing said metallization process in said void to form said contact comprises:

depositing at least one of a tungsten material or a cobalt material into said void; and

performing a CMP process.

11. A method, comprising:

forming a plurality of fins on a semiconductor substrate;

forming, over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion;

forming, over a second portion of the fins, a gate region;

performing a replacement metal gate (RMG) process in the gate region;

forming a trench in a portion of the gate region;

forming a void adjacent said a portion of said gate region;

forming a first carbon feature in said trench;

forming a carbon feature in said void;

performing a trench silicide (TS) cut process, forming a TS cut region;

removing said first carbon feature and filling said trench with a dielectric material;

removing said second carbon feature; and

performing a metallization process in said void to form a contact.

12. The method of claim 11 , wherein forming a trench in a portion of the gate region comprises:

forming a cap over said SAC; and

removing a first oxide layer from said TS cut region;

wherein forming said cap over said SAC comprises:

removing a portion of said SAC to form a recess in said SAC;

depositing a SOIC material into said recess in said SAC; and

performing a planarizing process on said SOIC material.

13. The method of claim 3 , wherein:

forming a void adjacent said a portion of said gate region comprises removing a second oxide layer from a region adjacent said cap and above said EPI feature;

forming said first carbon feature in said trench comprises depositing a carbon material into said trench and performing a chemical mechanical polishing (CMP) process on said carbon material; and

forming said carbon feature in said trench comprises depositing a carbon material into said void and performing a CMP process on said carbon material.

14. The method of claim 13 , wherein performing said TS cut process comprises:

depositing a oxide liner about said trench;

forming a nitride layer over said thin oxide liner; and

forming a oxide layer over said nitride layer.

15. The method of claim 14 , wherein removing said first carbon feature and filling said trench with a dielectric material comprises:

performing a carbon etch process in said TS cut region;

depositing an oxide material into said TS cut region;

removing said oxide liner, said nitride layer, and said oxide layer; and

performing a carbon etch to remove carbon material from said void.

16. The method of claim 15 , wherein removing said second carbon feature comprises:

removing said oxide liner, said nitride layer, and said oxide layer; and

performing a carbon etch to remove carbon material from said void.

17. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device comprising at least one fin field effect transistor (finFET); and

a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to:

form a plurality of fins on a semiconductor substrate;

form, over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion;

form, over a second portion of the fins, a gate region;

perform a replacement metal gate (RMG) process in the gate region;

form a trench in a portion of the gate region;

form a void adjacent said a portion of said gate region;

form, in said trench, a first pillar made of silicon or carbon;

form, in said void, a second pillar made of silicon or carbon;

form a TS cut region over said trench;

remove said first and second pillars; and

perform a metallization process in said void to form a contact.

18. The system of claim 17 , further comprising a design unit configured to generate a first design comprising a definition for a process mask, a definition for forming said trench and void, forming said first and second pillars, and performing said metallization process, wherein data from the design unit is used by the processing controller to control an operation of the semiconductor device processing system.

19. The system of claim 17 , wherein said system is further adapted to

deposit a oxide liner about said trench;

form a nitride layer over said thin oxide liner; and

form a oxide layer over said nitride layer.

20. The system of claim 19 , wherein said system is further adapted to:

perform at least one of a silicon etch process or a carbon etch process;

deposit an oxide material into said TS cut region;

remove said oxide liner, said nitride layer, and said oxide layer;

perform at least one of a silicon etch or a carbon etch to remove silicon material from said void.