Packaged semiconductor devices and methods of packaging semiconductor devices

1. A method comprising:

disposing a sacrificial layer over an integrated circuit die, the integrated circuit die having an upper surface extending from a first outermost edge of the integrated circuit die to a second outermost edge of the integrated circuit die, the sacrificial layer covering the upper surface;

disposing a first molding compound around the integrated circuit die and the sacrificial layer;

removing the sacrificial layer to form a step between the upper surface of the integrated circuit die and an upper surface of the first molding compound, the step having a non-zero step height;

forming a through via extending through the first molding compound; and

forming an interconnect structure over the integrated circuit die and the first molding compound, the interconnect structure electrically connecting the through via to the integrated circuit die.

2. The method of claim 1 , further comprising:

after disposing the sacrificial layer over the integrated circuit die, singulating the integrated circuit die and the sacrificial layer; and

placing the integrated circuit die on a carrier, the first molding compound dispensed on the carrier.

3. The method of claim 1 , further comprising:

singulating the interconnect structure and the first molding compound to form a first packaged semiconductor device.

4. The method of claim 3 , further comprising:

connecting the interconnect structure to a substrate with a plurality of conductors.

5. The method of claim 4 , further comprising:

disposing a second molding compound around the plurality of conductors.

6. The method of claim 5 , wherein disposing the second molding compound comprises disposing a liquid molding compound (LMC).

7. The method of claim 5 , further comprising:

dispensing an underfill material around the plurality of conductors, the underfill material extending from the second molding compound to the substrate.

8. The method of claim 3 , further comprising:

connecting a second packaged semiconductor device to the through via of the first packaged semiconductor device.

9. The method of claim 1 , wherein forming the interconnect structure comprises forming a redistribution layer (RDL) structure.

10. The method of claim 1 , wherein forming the interconnect structure comprises forming a post-passivation interconnect (PPI) structure.

11. The method of claim 1 , wherein the sacrificial layer comprises one of a photoresist material, an organic material, a polymer material, or combinations thereof.

12. A method comprising:

providing a wafer including a plurality of integrated circuit dies;

disposing a sacrificial layer on respective first surfaces of the integrated circuit dies;

singulating the integrated circuit dies, portions of the sacrificial layer disposed on each of the singulated integrated circuit dies;

disposing a first molding compound around the integrated circuit dies and the portions of the sacrificial layer, the first molding compound having a first surface that is co-planar with second surfaces of the portions of the sacrificial layer;

removing the portions of the sacrificial layer to form steps between the first surface of the first molding compound and the respective first surfaces of the integrated circuit dies, the steps each having a non-zero step height;

forming a plurality of through vias in the first molding compound; and

forming an interconnect structure over the integrated circuit dies and the first molding compound, the interconnect structure electrically connecting the through vias and the integrated circuit dies.

13. The method of claim 12 , further comprising:

coupling a plurality of conductors to the interconnect structure.

14. The method of claim 13 , further comprising:

singulating the interconnect structure and the first molding compound to form a plurality of packaged semiconductor devices, each of the plurality of packaged semiconductor devices including at least one of the integrated circuit dies and at least one of the through vias.

15. The method of claim 12 , wherein the sacrificial layer comprises one of a photoresist material, an organic material, a polymer material, or combinations thereof.

16. A method comprising:

forming a first sacrificial layer on a major surface of a first integrated circuit die;

forming a second sacrificial layer on a major surface of a second integrated circuit die;

placing the first integrated circuit die and the second integrated circuit die on a carrier such that each respective major surface faces the carrier;

encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound;

forming a plurality of through vias in the molding compound between the first integrated circuit die and the second integrated circuit die;

removing the carrier;

removing the first sacrificial layer to form a first step between the major surface of the first integrated circuit die and a major surface of the molding compound; and

removing the second sacrificial layer to form a second step between the major surface of the second integrated circuit die and the major surface of the molding compound.

17. The method of claim 16 , further comprising:

after removing the first sacrificial layer and the second sacrificial layer, singulating the first integrated circuit die and the second integrated circuit die.

18. The method of claim 16 , further comprising:

forming an interconnect structure over the first integrated circuit die and the second integrated circuit die, the interconnect structure electrically connected to the through vias.

19. The method of claim 18 , further comprising:

coupling a plurality of conductors to the interconnect structure.

20. The method of claim 16 , wherein the first sacrificial layer and the second sacrificial layer comprise one of a photoresist material, an organic material, a polymer material, or combinations thereof.