IP Library › Granted Patent US 10,269,791
Granted Patent B2
US 10,269,791 · App. 15/001,909 · Granted Apr 23, 2019

Field-effect transistors having transition metal dichalcogenide channels and methods of manufacture

Inventors: Yee-Chia Yeo (Hsin-Chu, TW); Ling-Yen Yeh (Hsin-Chu, TW); Yuan-Chen Sun (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/0886H01L21/02568H01L21/02614H01L21/02658H01L21/8256H01L29/24H01L29/66969H01L29/785
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Quick Facts
Patent No.
US 10,269,791
App. No.
15/001,909
Granted
Apr 23, 2019
Kind
B2
Abstract

A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

Claims (41)

1. A method of manufacturing a semiconductor device, the method comprising:

depositing a transition metal dichalcogenide material onto a substrate;

patterning the transition metal dichalcogenide material into one or more fins consisting of the transition metal dichalcogenide material, wherein each one of the one or more fins has a top surface parallel with the substrate and a sidewall extending between the top surface and the substrate;

depositing a gate dielectric layer overlying the one or more fins and in physical contact with the top surface and the sidewall;

depositing a gate electrode layer over the gate dielectric layer;

placing a mask over the gate electrode layer; and

patterning both the gate electrode layer and the gate dielectric layer to remove material exposed by the mask.

2. The method of claim 1 , wherein the depositing the transition metal dichalcogenide material further comprises:

introducing a first precursor material to the substrate; and

introducing a second precursor material to the substrate.

3. The method of claim 1 , wherein the sidewall is perpendicular to the substrate.

4. The method of claim 1 , wherein the sidewall is sloped with respect to the substrate.

5. The method of claim 1 , wherein the depositing the transition metal dichalcogenide material further comprises depositing a plurality of stacked, horizontally orientated layers.

6. The method of claim 1 , wherein the depositing the transition metal dichalcogenide material further comprises depositing a plurality of stacked, vertically orientated layers.

7. The method of claim 1 , wherein the depositing the transition metal dichalcogenide material further comprises depositing a polycrystalline material.

8. A method of manufacturing a semiconductor device, the method comprising:

reacting a first precursor to a second precursor to form a first transition metal dichalcogenide material over a substrate; and

forming a transistor from the first transition metal dichalcogenide material, the forming the transistor comprising:

patterning the first transition metal dichalcogenide material to form a fin consisting of the first transition metal dichalcogenide material;

forming a first gate dielectric in physical contact with and covering at least a portion of each one of exposed multiple sides of the fin

forming a gate electrode layer over the first gate dielectric;

forming a mask over the gate electrode layer; and

patterning both the gate electrode layer and the first gate dielectric to remove material exposed by the mask.

9. The method of claim 8 , wherein the reacting the first precursor to the second precursor forms a blanket layer of the first transition metal dichalcogenide material.

10. The method of claim 8 , wherein the multiple sides are perpendicular to the substrate.

11. The method of claim 8 , wherein the multiple sides are sloped with respect to the substrate.

12. The method of claim 8 , wherein the reacting the first precursor to the second precursor deposits a plurality of stacked, horizontally orientated layers.

13. The method of claim 8 , wherein the reacting the first precursor to the second precursor deposits a plurality of stacked, vertically orientated layers.

14. The method of claim 8 , wherein the reacting the first precursor to the second precursor deposits a polycrystalline material.

15. A method of manufacturing a semiconductor device, the method comprising:

depositing a transition metal dichalcogenide material onto a substrate;

patterning the transition metal dichalcogenide material into two or more fins consisting of the transition metal dichalcogenide material, wherein each one of the two or more fins has a top surface parallel with the substrate and a sidewall extending between the top surface and the substrate;

depositing a gate dielectric layer overlying the two or more fins and in physical contact with the top surface and the sidewall;

depositing a gate electrode layer over the gate dielectric layer;

placing a mask over the gate electrode layer; and

patterning both the gate electrode layer and the gate dielectric layer to remove material exposed by the mask.

16. The method of claim 15 , wherein the sidewall is sloped with respect to the substrate.

17. The method of claim 15 , wherein the depositing the transition metal dichalcogenide material further comprises depositing a plurality of stacked, horizontally orientated layers.

18. The method of claim 15 , wherein the depositing the transition metal dichalcogenide material further comprises depositing a plurality of stacked, vertically orientated layers.

19. The method of claim 15 , wherein the depositing the transition metal dichalcogenide material further comprises depositing a polycrystalline material.

20. The method of claim 15 , wherein the sidewall is perpendicular to the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: YEO, YEE-CHIA; YEH, LING-YEN; SUN, YUAN-CHEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 037711/0472 →
Continuity (2)
Provisional Application 62133813 · Mar 16, 2015
Related Publication 20160276343A1 · Sep 22, 2016
Cited By (2)
US 12,408,399 US 12,648,236