Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same

1. A method comprising:

forming first dummy gate stack and a second dummy gate stack over a semiconductor fin, wherein a portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack;

etching the portion of the semiconductor fin to extend the opening into the semiconductor fin, wherein a material of the semiconductor fin surrounds the opening in a top-down view of the semiconductor fin; and

epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.

2. The method of claim 1 , wherein epitaxially growing the source/drain region comprises epitaxially growing the source/drain region along sidewalls of the first dummy gate stack and the second dummy gate stack.

3. The method of claim 1 , wherein the first dummy gate stack further extends over an isolation region in a semiconductor substrate.

4. The method of claim 3 , wherein the first dummy gate stack extends from the semiconductor fin to an additional semiconductor fin, wherein the isolation region is disposed between the semiconductor fin and the additional semiconductor fin.

5. The method of claim 1 further comprising a third dummy gate stack disposed on an opposing side of the second dummy gate stack as the first dummy gate stack, wherein a first sidewall of the semiconductor fin is disposed under the first dummy gate stack, and wherein a second sidewall of the semiconductor fin opposite the first sidewall is disposed under the third dummy gate stack.

6. The method of claim 1 further comprising:

replacing the first dummy gate stack with a first replacement gate stack; and

replacing the second dummy gate stack with a second replacement gate stack.

7. The method of claim 6 , wherein the first replacement gate stack is a dummy gate stack, and wherein a dielectric layer covers an entire top surface of the first replacement gate stack after a gate contact is formed through the dielectric layer to electrically connect to the second replacement gate stack.

8. A method comprising:

forming a first dummy gate stack over an isolation region between a first semiconductor fin and a second semiconductor fin, wherein the first dummy gate stack extends from over a sidewall of the first semiconductor fin to over a sidewall of the second semiconductor fin, and wherein a first line along a lengthwise dimension of the first semiconductor fin extends through the first semiconductor fin and the second semiconductor fin;

etching a first opening in the first semiconductor fin adjacent the first dummy gate stack;

etching a second opening in the second semiconductor fin adjacent the first dummy gate stack;

epitaxially growing a first source/drain region in the first opening on the first semiconductor fin;

epitaxially growing a second source/drain region in the second opening on the second semiconductor fin; and

replacing the first dummy gate stack with a first replacement gate stack.

9. The method of claim 8 , wherein a material of the first semiconductor fin completely surrounds the first opening in a top-down view of the first semiconductor fin.

10. The method of claim 8 further comprising:

forming a second dummy gate stack adjacent the first dummy gate stack on the first semiconductor fin;

after epitaxially growing the first source/drain region, replacing the second dummy gate stack with a second replacement gate stack;

depositing a first dielectric layer over the first replacement gate stack and the second replacement gate stack; and

forming a gate contact extending through the first dielectric layer and electrically connected to the second replacement gate stack.

11. The method of claim 8 further comprising:

forming a second dielectric layer over the first source/drain region and the second source/drain region;

forming a first source/drain contact through the second dielectric layer and electrically connected to the first source/drain region; and

forming a second source/drain contact through the second dielectric layer and electrically connected to the second source/drain region.

12. The method of claim 8 , wherein the first dummy gate stack extends along sidewalls of the first semiconductor fin and the second semiconductor fin in a cross-sectional view taken along a second line perpendicular to the first line.

13. The method of claim 8 further comprising forming a spacer along a sidewall of the first dummy gate stack over the first semiconductor fin, wherein sidewalls of the first opening and the spacer are substantially aligned.

14. A method comprising:

forming a shallow trench isolation (STI) region between a first semiconductor fin and a second semiconductor fin;

depositing a dummy dielectric layer over the first semiconductor fin and the STI region;

depositing a dummy gate layer over the dummy dielectric layer;

patterning an opening extending through the dummy gate layer and dummy dielectric layer to expose a region of the first semiconductor fin, wherein after patterning the opening extending through the dummy gate layer and the dummy dielectric layer, first portions of the dummy dielectric layer and the dummy gate layer define a first dummy gate stack over the STI region;

extending the opening into the first semiconductor fin, wherein the opening is bounded on at least two sides by the first semiconductor fin in a top down view after extending the opening into the first semiconductor fin;

epitaxially growing a source/drain region over in the opening; and

after epitaxially growing the source/drain region, replacing the first dummy gate stack with a second dummy gate stack.

15. The method of claim 14 , wherein the first dummy gate stack extends continuously from a sidewall of the first semiconductor fin to a sidewall of the second semiconductor fin.

16. The method of claim 15 , wherein the first dummy gate stack is further disposed over the first semiconductor fin and the second semiconductor fin.

17. The method of claim 14 , wherein the opening is bounded all sides by the first semiconductor fin in the top down view after extending the opening into the first semiconductor fin.

18. The method of claim 14 , wherein after patterning the opening extending through the dummy gate layer and the dummy dielectric layer, second portions of the dummy dielectric layer and the dummy gate layer define a third dummy gate stack over the first semiconductor fin, wherein the method further comprises replacing the third dummy gate stack with a functional gate stack.

19. The method of claim 18 , wherein the functional gate stack and the second dummy gate stack are formed simultaneously.

20. The method of claim 14 further comprising forming a spacer along a sidewall of the first dummy gate stack over the first semiconductor fin, wherein sidewalls of the opening and the spacer are substantially aligned.