IP Library › Granted Patent US 10,269,950
Granted Patent B2
US 10,269,950 · App. 15/676,451 · Granted Apr 23, 2019

Compound semiconductor substrate and fabrication method therefor, compound semiconductor device and fabrication method therefor, power supply apparatus and high-output amplifier

Inventor: Atsushi Yamada (Isehara, JP)
Assignee: FUJITSU LIMITED
H01L29/7787H01L21/0254H01L21/0262H01L21/02378H01L21/02458H01L21/02505H01L23/3171H01L29/04H01L29/201H01L29/205H01L29/66462H01L29/7786H03F1/3247H03F3/195H03F3/245H01L23/3107H01L23/3114H01L23/4952H01L23/49513H01L23/49562H01L24/06H01L24/45H01L24/48H01L24/49H01L29/2003H01L2224/0603H01L2224/45124H01L2224/48247H01L2224/48257H01L2224/48472H01L2224/4903H01L2924/181H02M1/4208H02M1/4225H03F3/189H03F3/20H03F2200/451Y02B70/126
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Quick Facts
Patent No.
US 10,269,950
App. No.
15/676,451
Granted
Apr 23, 2019
Kind
B2
Abstract

A compound semiconductor substrate includes a substrate, a channel layer provided over the substrate, a nitride semiconductor layer provided over the channel layer, and a barrier layer provided on the nitride semiconductor layer. The length of the c axis of the nitride semiconductor layer is 0.4990 nm or more.

Claims (45)

1. A compound semiconductor substrate, comprising:

a substrate;

a channel layer provided over the substrate;

a spacer layer provided over the channel layer; and

a barrier layer provided on the spacer layer; wherein

a length of a c axis of the spacer layer is 0.4990 nm or more, and

the spacer layer have a higher Al composition than that of the barrier layer.

2. The compound semiconductor substrate according to claim 1 , wherein the spacer layer contains AlN.

3. The compound semiconductor substrate according to claim 1 , wherein the barrier layer contains In X1 Al y1 Ga 1-x1-y1 N (0<x1<0.20, 0<y1≤1).

4. The compound semiconductor substrate according to claim 1 , wherein the channel layer contains GaN.

5. The compound semiconductor substrate according to claim 1 , wherein a thickness of the spacer layer is 2 nm or less.

6. The compound semiconductor substrate according to claim 1 , wherein an arithmetical average roughness Ra of a surface of the barrier layer is 0.25 nm or less.

7. The compound semiconductor substrate according to claim 1 , further comprising a cap layer provided on the barrier layer.

8. The compound semiconductor substrate according to claim 7 , wherein the cap layer contains In x2 Al y2 Ga 1-x2-y2 N (0<x2<0.1, 0<y2≤0.05).

9. A compound semiconductor device, comprising:

a substrate;

a channel layer provided over the substrate;

a spacer layer provided over the channel layer;

a barrier layer provided on the spacer layer; and

a gate electrode, a source electrode and a drain electrode provided over the barrier layer; wherein

a length of a c axis of the spacer layer is 0.4990 nm or more, and

the spacer layer have a higher Al composition than that of the barrier layer.

10. The compound semiconductor device according to claim 9 , wherein the spacer layer contains AlN.

11. The compound semiconductor device according to claim 9 , wherein the barrier layer contains In X1 Al y1 Ga 1-x1-y1 N (0<x1<0.20, 0<y1≤1).

12. A power supply apparatus, comprising:

a transistor chip; wherein

the transistor chip includes:

a substrate;

a channel layer provided over the substrate;

a spacer layer provided over the channel layer;

a barrier layer provided on the spacer layer; and

a gate electrode, a source electrode and a drain electrode provided over the barrier layer; wherein

a length of a c axis of the spacer layer is 0.4990 nm or more, and

the spacer layer have a higher Al composition than that of the barrier layer.

13. A high-output amplifier, comprising:

an amplifier that amplifies an inputting signal; wherein

the amplifier includes a transistor chip;

the transistor chip includes:

a substrate;

a channel layer provided over the substrate;

a spacer layer provided over the channel layer;

a barrier layer provided on the spacer layer; and

a gate electrode, a source electrode and a drain electrode provided over the barrier layer; wherein

a length of a c axis of the spacer layer is 0.4990 nm or more, and

the spacer layer have a higher Al composition than that of the barrier layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2017
From: YAMADA, ATSUSHI
To: FUJITSU LIMITED
Reel/Frame 043543/0906 →
Priority Claims (1)
JP 2016-189942 · Sep 28, 2016 · national
Continuity (1)
Related Publication 20180090603A1 · Mar 29, 2018