Electrostatic discharge protection circuit

1. An ESD protection circuit, comprising:

an input port;

a resistor;

a BJT, having an emitter, a base, and a collector, wherein the emitter of the BJT is coupled to the input port, and the base of the BJT is coupled through the resistor to the input port; and

a diode, having a first terminal and a second terminal, wherein the first terminal of the diode is the collector of the BJT, and the second terminal of the diode is coupled to a supply voltage;

wherein the resistor is a two-port element or a multi-port element which has a first terminal coupled to the base of the BJT and a second terminal coupled to the emitter of the BJT;

wherein when a positive voltage is applied to the input port, the resistor is capable of clamping a junction voltage between the emitter and the base of the BJT.

2. The ESD protection circuit as claimed in claim 1 , wherein the emitter of the BJT is formed by a first type-I semiconductor, the base of the BJT is formed by a first type-II semiconductor, the collector of the BJT is formed by a second type-I semiconductor, and the diode is formed by the second type-I semiconductor and a second type-II semiconductor.

3. The ESD protection circuit as claimed in claim 2 , wherein:

the first type-I semiconductor is a high-doped P-type semiconductor, the first type-II semiconductor is an N-type semiconductor, the second type-I semiconductor is a low-doped P-type semiconductor, and the second type-II semiconductor is an N-type semiconductor; or

the first type-I semiconductor is a high-doped N-type semiconductor, the first type-II semiconductor is a P-type semiconductor, the second type-I semiconductor is a low-doped N-type semiconductor, and the second type-II semiconductor is a P-type semiconductor.

4. The ESD protection circuit as claimed in claim 1 , wherein the BJT is a heterojunction bipolar transistor (HBT).

5. The ESD protection circuit as claimed in claim 1 , wherein a resistance of the resistor is from about 100Ω to about 100 kΩ.

6. An ESD protection circuit, comprising:

an input port;

a first resistor;

a second resistor;

a first BJT, having an emitter, a base, and a collector, wherein the emitter of the first BJT is coupled to the input port, and the base of the first BJT is coupled through the first resistor to the input port; and

a second BJT, having an emitter, a base, and a collector, wherein the emitter of the second BJT is coupled to a supply voltage, the base of the second BJT is coupled through the second resistor to the supply voltage, and the collector of the second BJT is the collector of the first BJT;

wherein when a positive voltage is applied to the input port, the first resistor is capable of clamping a junction voltage between the emitter and the base of the first BJT;

wherein when a negative voltage is applied to the input port, the second resistor is capable of clamping a junction voltage between the emitter and the base of the second BJT.

7. The ESD protection circuit as claimed in claim 6 , wherein the emitter of the first BJT is formed by a first type-I semiconductor, the base of the first BJT is formed by a first type-II semiconductor, the emitter of the second BJT is formed by a second type-I semiconductor, the base of the second BJT is formed by a second type-II semiconductor, and both the collector of the first BJT and the collector of the second BJT are formed by a third type-I semiconductor.

8. The ESD protection circuit as claimed in claim 7 , wherein:

the first type-I semiconductor and the second type-I semiconductor are each a high-doped N-type semiconductor, the first type-II semiconductor and the second type-II semiconductor are each a P-type semiconductor, and the third type-I semiconductor is a low-doped N-type semiconductor; or

the first type-I semiconductor and the second type-I semiconductor are each a high-doped P-type semiconductor, the first type-II semiconductor and the second type-II semiconductor are each an N-type semiconductor, and the third type-I semiconductor is a low-doped P-type semiconductor.

9. The ESD protection circuit as claimed in claim 7 , wherein the ESD protection circuit further comprises a type-II semiconductor substrate, the third type-I semiconductor is disposed on the type-II semiconductor substrate, and the type-II semiconductor substrate is coupled to the supply voltage.

10. The ESD protection circuit as claimed in claim 6 , wherein each BJT is a heterojunction bipolar transistor (HBT).

11. The ESD protection circuit as claimed in claim 6 , wherein each resistor is a two-port element or a multi-port element.

12. The ESD protection circuit as claimed in claim 6 , wherein a resistance of each resistor is from about 100Ω to about 100 kΩ.

13. An ESD protection circuit, comprising:

an input port;

a resistor;

a BJT, having an emitter, a base, and a collector, wherein the emitter of the BJT is coupled to the input port, and the base of the BJT is coupled through the resistor to the input port; and

a diode, having a first terminal and a second terminal, wherein the first terminal of the diode is the collector of the BJT, and the second terminal of the diode is coupled to a supply voltage;

wherein the emitter of the BJT is formed by a first type-I semiconductor, the base of the BJT is formed by a first type-II semiconductor, the collector of the BJT is formed by a second type-I semiconductor, and the diode is formed by the second type-I semiconductor and a second type-II semiconductor;

wherein:

the first type-I semiconductor is a high-doped P-type semiconductor, the first type-II semiconductor is an N-type semiconductor, the second type-I semiconductor is a low-doped P-type semiconductor, and the second type-II semiconductor is an N-type semiconductor; or

the first type-I semiconductor is a high-doped N-type semiconductor, the first type-II semiconductor is a P-type semiconductor, the second type-I semiconductor is a low-doped N-type semiconductor, and the second type-II semiconductor is a P-type semiconductor.