Method of semiconductor device fabrication

1. A method for fabricating a semiconductor device, the method comprising:

depositing a dielectric layer having a first thickness directly on a substrate, wherein the first thickness defines a target isolation feature thickness;

depositing a hard mask (HM) layer having a second thickness directly on the dielectric layer, wherein the second thickness defines a target fin feature height;

forming a first fin trench and a second fin trench that extend through the HM layer and the dielectric layer to expose the substrate;

forming a first masking layer that covers a first region of the HM layer that includes the second fin trench, wherein the first masking layer fills the second fin trench;

forming a first semiconductor material that covers at least a portion of a second region of the HM layer that includes the first fin trench, wherein the first semiconductor material fills the first fin trench;

forming a second masking layer that covers the first semiconductor material and the second region of the HM layer;

after removing the first masking layer, forming a second semiconductor material that covers at least a portion of the first region of the HM layer that includes the second fin trench, wherein the second semiconductor material fills the second fin trench and the second semiconductor material is different than the first semiconductor material;

after removing the second masking layer, performing a planarization process that removes the first semiconductor material and the second semiconductor material covering the HM layer, thereby forming a first fin feature having the target fin feature height and a second fin feature having the target fin feature height; and

removing the HM layer to expose an upper portion of the first fin feature and an upper portion of the second fin feature, wherein a height of the upper portion of the first fin feature and a height of the upper portion of the second fin feature are substantially equal to the second thickness and a portion of the dielectric layer defines a first isolation feature having the isolation feature target thickness adjacent to the first fin feature and a second isolation feature having the isolation feature target thickness adjacent to the second fin feature.

2. The method of claim 1 , wherein the target fin feature height is greater than the first thickness.

3. The method of claim 1 , wherein the forming the first masking layer includes forming a first patterned resist layer and the forming the second masking layer includes forming a second patterned resist layer.

4. The method of claim 1 , wherein the forming the first fin trench and the second fin trench includes:

forming a sacrificial layer directly on the HM layer, wherein the sacrificial layer includes a first opening defining a first fin feature target width for the first fin feature and a second opening defining a second fin feature target width for the second fin feature; and

etching the HM layer and dielectric layer exposed by the first opening and the second opening.

5. The method of claim 4 , wherein the forming the sacrificial layer directly on the HM layer includes:

forming a first spacer and a second spacer directly on the HM layer, wherein a width of the first spacer is substantially equal to the first fin feature target width and a width of the second spacer is substantially equal to the second fin feature target width;

depositing the sacrificial layer directly on the HM layer, wherein the sacrificial layer covers the first spacer and the second spacer;

etching back the sacrificial layer to expose the first spacer and the second spacer; and

selectively removing the first spacer and the second spacer, thereby forming the first opening and the second opening in the sacrificial layer.

6. The method of claim 5 , wherein the forming the first spacer and the second spacer directly on the HM layer includes:

forming a first mandrel feature and a second mandrel feature directly on the HM layer;

forming the first spacer along a sidewall of the first mandrel feature and the second spacer along a sidewall of the second mandrel feature, wherein the width of the first spacer is less than a width of the first mandrel feature and the width of the second spacer is less than a width of the second mandrel feature; and

selectively removing the first mandrel feature and the second mandrel feature.

7. The method of claim 1 , wherein the forming the first semiconductor material and the forming the second semiconductor material includes:

epitaxially growing the first semiconductor material from the substrate to fill in the first fin trench until the the first semiconductor material extends over the HM layer in the second region of the HM layer; and

epitaxially growing the second semiconductor material from the substrate to fill in the second fin trench until the the second semiconductor material extends over the HM layer in the second region of the HM layer.

8. The method of claim 1 , wherein the HM layer is removed by a selective etch that does not substantially etch the first fin feature, the second fin feature, and the dielectric layer.

9. The method of claim 1 , wherein the first fin trench and the second fin trench is further formed through a portion of the substrate.

10. The method of claim 1 , wherein before removing the HM layer, a top surface of the first fin feature and a top surface of the second fin feature is substantially planar with a top surface of the HM layer.

11. A method for fabricating a semiconductor device, the method comprising:

depositing a dielectric layer over a semiconductor substrate;

depositing a hard mask (HM) layer over the dielectric layer;

forming a mandrel feature over the HM layer;

forming a spacer along a sidewall of the mandrel feature;

selectively removing the mandrel feature;

depositing a sacrificial layer over the spacer;

etching back the sacrificial layer to expose the spacer;

selectively removing the spacer to form an opening in the sacrificial layer;

etching the HM layer and dielectric layer through the opening and extending etching down to the semiconductor substrate to form a first fin trench, wherein the etching of the HM layer and the dielectric layer includes forming a second fin trench adjacent the first fin trench, the second fin trench extending through the HM layer, the dielectric and to the semiconductor substrate;

forming a first semiconductor feature in the first fin trench and over the HM layer, wherein forming the first semiconductor feature in the first fin trench includes forming a first semiconductor material directly on the semiconductor substrate such that the first semiconductor material extends form the semiconductor substrate to at least over the HM layer;

forming a second semiconductor feature in the second fin trench and over the HM layer, wherein forming the second semiconductor feature in the second fin trench includes forming a second semiconductor material directly on the semiconductor substrate such that the second semiconductor material extends form the semiconductor substrate to over the HM layer such that a first portion of the second semiconductor material directly interfaces with a first portion of the first semiconductor material formed over the HM layer, the second semiconductor material being different than the first semiconductor material; and

removing the HM layer and the first portions of the first and second semiconductor materials to expose a second portion of the first semiconductor material to form a first fin feature, to expose a second portion of the second semiconductor material to form a second fin feature and to expose a top surface of the dielectric layer, the top surface of the dielectric layer facing away from the semiconductor substrate and the semiconductor material extending to the semiconductor substrate after the removal of the HM layer.

12. The method of claim 11 , wherein etching the HM layer and dielectric layer through the opening and extending etching down to the semiconductor substrate to form the first fin trench includes etching a portion of the semiconductor substrate such that the first fin trench extends into the semiconductor substrate.

13. The method of claim 11 , wherein etching back the sacrificial layer to expose the spacer includes recessing the sacrificial layer such that a top surface of the sacrificial layer is below a top surface of the spacer.

14. A method comprising:

forming a dielectric layer over a semiconductor substrate;

forming a hard mask layer over the dielectric layer;

forming a patterned first material layer over hard mask layer;

forming a second material layer on the patterned first material layer;

removing the patterned first material layer to form a patterned second material layer;

forming a first trench and a second trench extending thorough the hard mask layer, the dielectric layer, and into the semiconductor substrate by using the patterned second material layer as a mask;

forming a first semiconductor feature in the first trench and over the hard mask layer, wherein forming the first semiconductor feature in the first trench includes forming a semiconductor material directly on the semiconductor substrate such that the semiconductor material extends form the semiconductor substrate to at least over the hard mask layer;

forming a second semiconductor feature in the second trench and over the hard mask layer such that the second semiconductor feature directly interfaces with the first semiconductor feature over the hard mask layer, the second semiconductor feature being formed of a different semiconductor material than the first semiconductor feature; and

removing the hard mask layer, a first portion of the first semiconductor feature and a first portion of the second semiconductor feature to expose a second portion of the first semiconductor feature, to expose a second portion of the second semiconductor feature and to expose a top surface of the dielectric layer, the top surface of the dielectric layer facing away from the semiconductor substrate and the semiconductor material extending to the semiconductor substrate after the removal of the hard mask layer.

15. The method of claim 14 , wherein forming the first trench extending thorough the hard mask layer, the dielectric layer, and into the semiconductor substrate by using the patterned second material layer as the mask includes forming a third trench extending thorough the hard mask layer, the dielectric layer, and into the semiconductor substrate, and

wherein forming the first semiconductor feature in the first trench further includes forming a third semiconductor feature in the second trench.

16. The method of claim 15 , wherein the first and third semiconductor features are formed of the same semiconductor material.

17. The method of claim 15 , wherein the first semiconductor feature has a first sidewall disposed in the semiconductor substrate and the second semiconductor feature has a second sidewall disposed in the semiconductor substrate, and

wherein a portion of the semiconductor substrate extends continuously from the first sidewall to the second sidewall.

18. The method of claim 14 , wherein forming the first semiconductor feature in the first trench includes performing an epitaxial growth process.

19. The method of claim 14 , wherein the first trench includes a first sidewall formed of the semiconductor substrate and an opposing second sidewall formed of the semiconductor substrate, and

wherein after forming the first semiconductor feature in the first trench the first semiconductor feature extends from the first sidewall formed of the semiconductor substrate to the opposing second sidewall formed of the semiconductor substrate.

20. The method of claim 14 , wherein forming the dielectric layer over the semiconductor substrate includes forming the dielectric layer directly on the semiconductor substrate such that the dielectric layer physically contacts the semiconductor substrate, and

wherein forming the hard mask layer over the dielectric layer includes forming the hard mask layer directly on the dielectric layer such that the hard mask layer physically contacts the dielectric layer.