Semiconductor package assembly

1. A semiconductor package assembly, comprising:

a core substrate formed of a first material having a device-attach surface and a solder-bump-attach surface opposite to the die-attach surface;

a bump pad disposed on the bump-attach surface; and

a first solder mask layer formed of the first material covering the bump-attach surface of the core substrate and a portion of the bump pad;

a second solder mask layer covering the device-attach surface of the core substrate, wherein the second solder mask layer is formed of a second material; and

a device pad disposed on the device-attach surface of the core substrate, wherein the device pad is exposed from and surrounded by a second opening of the second solder mask layer with the device pad being separated from second solder mask layer.

2. The semiconductor package assembly as claimed in claim 1 , wherein the second material is different from the first material.

3. The semiconductor package assembly as claimed in claim 2 , wherein the first material comprises a thermosetting material, and the second material comprises a photocuring material.

4. The semiconductor package assembly as claimed in claim 1 , wherein the first material comprises polypropylene (PP) resin or Ajinomoto build-up film (ABF).

5. The semiconductor package assembly as claimed in claim 1 , wherein the first material layer comprises glass fibers dispersed therein.

6. The semiconductor package assembly as claimed in claim 1 , wherein the second material comprises a photoimageable solder mask material.

7. The semiconductor package assembly as claimed in claim 1 , further comprising:

a first conductive trace disposed on the device-attach surface and covered by the second solder mask layer;

a second conductive trace disposed on the bump-attach surface and covered by the first solder mask layer;

a through via plug passing through the core substrate, wherein the through via plug is electrically connected to the first conductive trace and the second conductive trace.

8. The semiconductor package assembly as claimed in claim 1 , further comprising:

a conductive plug structure embedded in the core substrate, wherein the bump pad is a portion of the conductive plug structure, and a boundary of the bump pad is aligned to a boundary of the conductive plug structure.

9. The semiconductor package assembly as claimed in claim 1 , wherein the bump pad is exposed from a first opening of the first solder mask layer, and the first opening is adjacent to the bump pad.

10. The semiconductor package assembly as claimed in claim 1 , further comprising a solder cap disposed in the second opening between the device pad and the second solder mask layer.

11. A semiconductor package assembly, comprising:

a core substrate having a first surface and a second surface opposite to the first surface;

a first pad disposed on the first surface of the core substrate;

a solder mask layer covering the first surface of the core substrate; and

a conductive plug structure having a top portion on the first surface of the core substrate and a bottom portion between the first surface and the second surface of the core substrate;

wherein the pad is exposed from and surrounded by an opening of the solder mask layer with the device pad being separated from solder mask layer.

12. The semiconductor package assembly as claimed in claim 11 , wherein the core substrate comprises a trench formed extended into a portion of the core substrate form the second surface of the core substrate, and the bottom portion of the conductive plug structure is exposed to a bottom of the trench.

13. The semiconductor package assembly as claimed in claim 11 , wherein the conductive plug structure covers the first surface of the core substrate and extended into the core substrate.

14. The semiconductor package assembly as claimed in claim 11 , wherein the bottom portion serves as a second pad close to the second surface.

15. The semiconductor package assembly as claimed in claim 14 , wherein the core substrate is formed of a first material, the solder mask layer is formed of a second material that is different from the first material.

16. The semiconductor package assembly as claimed in claim 11 , wherein the core substrate and the solder mask layer are formed of the same material.

17. The semiconductor package assembly as claimed in claim 15 , wherein the first material comprises a thermosetting material, and the second material comprises a photocuring material.

18. The semiconductor package assembly as claimed in claim 15 , wherein the first material comprises polypropylene (PP) resin or Ajinomoto build-up film (ABF).

19. The semiconductor package assembly as claimed in claim 15 , wherein the first material layer comprises glass fibers dispersed therein.

20. The semiconductor package assembly as claimed in claim 15 , wherein the second material comprises a photoimageable solder mask material.

21. The semiconductor package assembly as claimed in claim 11 , further comprising a solder cap disposed in the opening between the pad and the solder mask layer.

22. A semiconductor package assembly, comprising:

a base, comprising:

a core substrate formed of a first material having device-attach surface and a solder-bump-attach surface opposite to the device-attach surface;

a first solder mask layer formed of the first material covering the solder-bump-attach surface of the core substrate; and

a bump pad on the solder-bump-attach surface of the core substrate, wherein the bump pad is exposed to an opening of the first solder mask layer;

a solder-bump structure in contact with first solder mask layer and electrically connected to the bump pad;

a second solder mask layer covering the device-attach surface of the base and disposed between the semiconductor device and the base; and

a device pad disposed on the second surface of the core substrate, wherein the device pad is exposed from and surrounded by a second opening of the second solder mask layer with the device pad being separated from second solder mask layer.

23. The semiconductor package assembly as claimed in claim 22 , further comprising:

a semiconductor device disposed on the device-attach surface of the core substrate and electrically coupled to a device pad of the base, wherein the device pad is disposed on the device-attach surface of the base.

24. The semiconductor package assembly as claimed in claim 23 , further comprising:

a first conductive trace disposed on the device-attach surface and covered by the second solder mask layer;

a second conductive trace disposed on the bump-attach surface and covered by the first solder mask layer;

a through via plug passing through the core substrate, wherein the through via plug is electrically connected to the first conductive trace and the second conductive trace.

25. The semiconductor package assembly as claimed in claim 23 , further comprising:

a via plug structure embedded in the core substrate, wherein the bump pad is a portion of the through via plug, and a boundary of the bump pad is aligned to a boundary of the via plug structure.

26. The semiconductor package assembly as claimed in claim 23 , wherein the second solder mask layer is formed of a second material that is different from the first material.

27. The semiconductor package assembly as claimed in claim 26 , wherein the first material comprises polypropylene (PP) resin or Ajinomoto build-up film (ABF).

28. The semiconductor package assembly as claimed in claim 26 , wherein the first solder mask layer comprises glass fibers dispersed therein.

29. The semiconductor package assembly as claimed in claim 26 , wherein the second material comprises a photoimageable solder mask material.