Low warpage high density trench capacitor
A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.
1. A semiconductor die, comprising:
a plurality of capacitor structures defined in a substrate, wherein each of the plurality of capacitor structures comprises:
a two-dimensional trench array having a plurality of segments defined therein, wherein the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array, and wherein each of the plurality of segments comprises an array of a plurality of recesses having a predetermined length extending along a surface of the substrate;
a first dielectric layer contacting a bottom region and sidewalls of the plurality of recesses and the surface of the substrate;
a first conducting layer of a first thickness disposed over the bottom region and sidewalls of the plurality of recesses and over the surface of the substrate, wherein the first conducting layer is insulated from the substrate by the first dielectric layer; and
a second conducting layer disposed over the first conducting layer and insulated from the first conducting layer by a second dielectric layer.
2. The semiconductor die of claim 1 , wherein the plurality of segments comprise a first array extending in first direction and a second array extending in a second direction, wherein the first direction is generally perpendicular to the second direction.
3. The semiconductor die of claim 2 , wherein each capacitor structure comprises two first arrays and two second arrays, wherein each of the first arrays are diametrically opposed to one another about the center of the respective capacitor structure, and wherein each of the second arrays are diametrically opposed to one another about the center of the respective capacitor structure, wherein the two first arrays and two second arrays define a rotationally symmetric layout.
4. The semiconductor die of claim 1 , wherein the second conducting layer fills a remainder of the plurality of recesses not filled by the first conducting layer while maintaining an air gap between the sidewalls of the respective plurality of recesses.
5. The semiconductor die of claim 1 , further comprising:
a first contact connected to the first conducting layer over the surface of the substrate;
a second contact connected to the second conducting layer; and
a third contact connected to the substrate within a local region to the plurality of capacitor structures.
6. The semiconductor die of claim 5 , wherein the substrate comprises a p-type silicon substrate, and wherein the local region comprises an n-type doped region within a vicinity of the plurality of capacitor structures.
7. The semiconductor die of claim 1 , wherein the first and second conducting layers comprise polysilicon.
8. The semiconductor die of claim 1 , wherein the first and second dielectric layers comprise oxide/nitride/oxide.
9. The semiconductor die of claim 1 , wherein the plurality of capacitor structures are electronically coupled to an integrated circuit by a wire bond, a through silicon via, or a bond pad.
10. The semiconductor die of claim 1 , wherein the plurality of capacitor structures reside within a dynamic random-access memory storage cell.
11. A semiconductor die, comprising:
a plurality of capacitor structures defined in a substrate, wherein each of the plurality of capacitor structures comprises:
a two-dimensional trench array having a plurality of segments defined therein, wherein the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array, and wherein each of the plurality of segments comprises an array of a plurality of recesses having a predetermined length extending along a surface of the substrate;
a first dielectric layer contacting a bottom region and sidewalls of the plurality of recesses and the surface of the substrate;
a first conducting layer of a first thickness disposed over the bottom region and sidewalls of the plurality of recesses and over the surface of the substrate, wherein the first conducting layer is insulated from the substrate by the first dielectric layer; and
a second conducting layer disposed over the first conducting layer and insulated from the first conducting layer by a second dielectric layer, wherein the second conducting layer fills a remainder of the plurality of recesses not filled by the first conducting layer while maintaining an air gap between the sidewalls of the respective plurality of recesses.
12. The semiconductor die of claim 11 , wherein the plurality of segments comprise a first array extending in first direction and a second array extending in a second direction, wherein the first direction is generally perpendicular to the second direction.
13. The semiconductor die of claim 12 , wherein each of the plurality of capacitor structures comprises two first arrays and two second arrays, wherein each of the first arrays are diametrically opposed to one another about the center of the respective capacitor structure, and wherein each of the second arrays are diametrically opposed to one another about the center of the respective capacitor structure, wherein the two first arrays and two second arrays define a rotationally symmetric layout.
14. The semiconductor die of claim 11 , further comprising:
a first contact connected to the first conducting layer over the surface of the substrate;
a second contact connected to the second conducting layer; and
a third contact connected to the substrate within a local region to the plurality of capacitor structures.
15. The semiconductor die of claim 14 , wherein the substrate comprises a p-type silicon substrate, and wherein the local region comprises an n-type doped region within a vicinity of the plurality of capacitor structures.
16. The semiconductor die of claim 11 , wherein the first and second conducting layers comprise polysilicon.
17. The semiconductor die of claim 11 , wherein the first and second dielectric layers comprise oxide/nitride/oxide.
18. The semiconductor die of claim 11 , wherein the plurality of capacitor structures are electronically coupled to an integrated circuit by a wire bond, a through silicon via, or a bond pad.
19. The semiconductor die of claim 11 , further comprising a dynamic random-access memory storage cell, wherein the plurality of capacitor structures reside within the dynamic random-access memory storage cell.
20. A semiconductor die, comprising:
a plurality of capacitor structures defined within a substrate, wherein each of the plurality of capacitor structures comprises:
a doped region of the substrate having a two-dimensional trench array defined therein, the two-dimensional array having a plurality of segments defined therein, wherein each of the plurality of segments comprises an array of a plurality of recesses in the substrate having a predetermined length extending along a surface of the substrate, and wherein the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array;
a first dielectric layer contacting a bottom region and sidewalls of the plurality of recesses and the surface of the substrate;
a first conducting layer of a first thickness disposed over the bottom region and sidewalls of the plurality of recesses and over the surface of the substrate, wherein the first conducting layer is insulated from the substrate by the first dielectric layer;
a second dielectric layer; and
a second conducting layer disposed over the first conducting layer and insulated from the first conducting layer by the second dielectric layer.