Self-aligned inner-spacer replacement process using implantation

1. A method for manufacturing a semiconductor device, comprising:

forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer;

forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region;

performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration;

forming a first spacer layer on each of the plurality of dummy gates, and on the exposed portions of the stacked configuration in the source/drain regions;

removing horizontal portions of the first spacer layer and parts of the stacked configuration under the horizontal portions of the first spacer layer;

selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region to form a plurality of openings, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region, and the selective removal occurs after forming the first spacer layer and after removing the horizontal portions of the first spacer layer and the parts of the stacked configuration; and

forming a second spacer layer in each of the plurality of openings left after selectively removing the first semiconductor layers from the source/drain region;

wherein the implantation is performed at a temperature greater than about 400° C. in order to avoid an amorphization.

2. The method according to claim 1 , wherein the selective removal stops at the first semiconductor layers in the channel region.

3. The method according to claim 1 , wherein the selective removal comprises a lateral wet etch process.

4. The method according to claim 3 , wherein the selective removal is performed using an etchant comprising a NH 4 OH:H 2 O 2 solution.

5. The method according to claim 1 , wherein the implantation increases the concentration of the semiconductor material in the exposed portions of the stacked configuration by 5% or more than 5%.

6. The method according to claim 1 , wherein the implantation is performed using a plurality of implantation steps.

7. The method according to claim 6 , wherein each step of the plurality of implantation steps is performed at a different energy level.

8. The method according to claim 1 , wherein the first and second semiconductor layers respectively comprise silicon germanium and silicon.

9. The method according to claim 1 , wherein the semiconductor material for the implantation comprises germanium.

10. A method for manufacturing a semiconductor device, comprising:

forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer;

forming a dummy gate on the stacked configuration, wherein the dummy gate covers a portion of the stacked configuration in a channel region;

performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration;

forming a first spacer layer on the dummy gate, and on the exposed portions of the stacked configuration in the source/drain regions;

removing horizontal portions of the first spacer layer and parts of the stacked configuration under the horizontal portions of the first spacer layer; and

selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region to form a plurality of openings, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region, and the selective removal occurs after forming the first spacer layer and after removing the horizontal portions of the first spacer layer and the parts of the stacked configuration; and

forming a second spacer layer in each of the plurality of openings left after selectively removing the first semiconductor layers from the source/drain region;

wherein the implantation is performed at a temperature greater than about 400° C. in order to avoid an amorphization.

11. The method according to claim 10 , wherein the selective removal stops at the first semiconductor layers in the channel region.

12. The method according to claim 10 , wherein the selective removal comprises a lateral wet etch process.

13. The method according to claim 12 , wherein the selective removal is performed using an etchant comprising a NH 4 OH:H 2 O 2 solution.

14. The method according to claim 10 , wherein the first and second semiconductor layers respectively comprise silicon germanium and silicon.

15. The method according to claim 10 , wherein the semiconductor material for the implantation comprises germanium.