Testing circuit of a longtime-constant circuit stage and corresponding testing method
A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
1. A test circuit comprising:
a charge-retention circuit for measurement of a time interval, the charge-retention circuit comprising a storage capacitor connected between a first biasing terminal and a floating node, and a discharge element connected between the floating node and a reference terminal, the discharge element configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric,
a biasing stage, configured to bias the floating node at a reading voltage;
a detection stage configured to detect a biasing value of the reading voltage; and
an integrator stage, including a test capacitor coupled to the floating node, configured to implement an operation of integration of a discharge current in the discharge element with the reading voltage kept constant at the biasing value, and to determine an effective resistance value of the discharge element as a function of the operation of integration.
2. The test circuit according to claim 1 , wherein the biasing stage comprises a shifting stage, configured to carry out shifting of the value of the reading voltage of the floating node, from a negative value to a positive value, before the detection stage detects a biasing value thereof.
3. The test circuit according to claim 2 , wherein the shifting stage comprises:
a generator stage configured to generate a shifting voltage; and
a switching stage, configured to receive the shifting voltage and switch a voltage of the first biasing terminal and second biasing terminal from a reference voltage to the shifting voltage, following upon biasing of the floating node at the reading voltage.
4. The test circuit according to claim 1 , further comprising:
a first discharge resistor coupled between the first biasing terminal and a ground node set at a ground voltage, wherein a resistance value of the first discharge resistor is lower than a resistance value of the discharge element by at least one order of magnitude; and
a second discharge resistor coupled between a second biasing terminal and a ground node, wherein a resistance value of the second discharge resistor is lower than the resistance value of the discharge element by at least one order of magnitude.
5. The test circuit according to claim 1 , wherein the biasing stage comprises a switching stage, configured to receive a positive biasing voltage and a negative biasing voltage and switch a respective biasing voltage of the first biasing terminal and a second biasing terminal to the value of the positive biasing voltage, or of the negative biasing voltage, so as to inject charges into, or extract charges from, the storage capacitor.
6. The test circuit according to claim 1 , wherein the charge-retention circuit further comprises a transfer capacitor coupled between a second biasing terminal and the floating node, wherein the transfer capacitor is configured to inject charges into, or extract charges from, the storage capacitor by a tunnel effect.
7. An electronic device, comprising:
a supervision unit;
a non-volatile memory operatively coupled to the supervision unit; and
the test circuit according to claim 1 operatively coupled to the supervision unit.
8. An electrical testing system, comprising:
the test circuit according to claim 1 ; and
an electrical testing apparatus, operatively coupled to the test circuit for implementing a test procedure designed to determine an effective value of the resistance of the discharge element of the charge-retention circuit and to adjust accordingly the value of a comparison reference voltage, to obtain a desired value of duration of a discharge interval associated to the discharge element.
9. A test circuit comprising:
a charge-retention circuit for measurement of a time interval, the charge-retention circuit comprising a storage capacitor connected between a first biasing terminal and a floating node, and a discharge element connected between the floating node and a reference terminal, the discharge element configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric,
a biasing stage, configured to bias the floating node at a reading voltage;
a detection stage configured to detect a biasing value of the reading voltage; and
an integrator stage, including a test capacitor coupled to the floating node, configured to implement an operation of integration of a discharge current in the discharge element with the reading voltage kept constant at the biasing value, and to determine an effective resistance value of the discharge element as a function of the operation of integration, wherein the integrator stage further comprises an operational amplifier, having a first input terminal connected to the floating node and configured to receive the reading voltage, a second input terminal configured to receive a comparison reference voltage, the value of which is kept constant at the biasing value during the operation of integration, and an output terminal on which it is configured to supply an output voltage, wherein the test capacitor is selectively connected between the first input terminal and the output terminal during the operation of integration.
10. The test circuit according to claim 9 , wherein the output voltage, during the operation of integration, has a voltage variation in a measurement time interval, and wherein the effective resistance value is a function according to the expression
R
L
′
~
V
x
(
t
0
)
Δ
V
out
·
Δ
T
C
T
where R L ′ is the effective resistance value, ΔVout is the voltage variation, ΔT is the measurement time interval, Vx(to) is the constant value of the comparison reference voltage, and C T is a capacitance value of the test capacitor.
11. The test circuit according to claim 9 , wherein the detection stage comprises:
a control unit; and
a reference-variation stage coupled to the control unit and controlled by the control unit for varying iteratively the value of the comparison reference voltage supplied to the second input terminal of the operational amplifier, which is configured to operate as a comparator, wherein, upon switching of the output voltage of the operational amplifier, the value of the comparison reference voltage corresponds to the biasing value.
12. The test circuit according to claim 11 , wherein the detection stage further comprises a non-volatile memory coupled to the control unit and configured to store the value of the comparison reference voltage corresponding to the biasing value.
13. The test circuit according to claim 11 , wherein the reference-variation stage comprises a digital-to-analog converter configured to generate, with successive incremental steps, incremental values of the comparison reference voltage according to a staircase ramp pattern.
14. The test circuit according to claim 9 , further comprising:
a coupling switch element connected between the first biasing terminal and an internal node and driven by a test control signal, wherein the test capacitor is connected between the floating node and the internal node; and
a feedback switch element connected between the internal node and an output terminal of the operational amplifier and driven by a negated version of the test control signal.
15. The test circuit according to claim 14 , wherein a capacitance value of the test capacitor is a fraction of a respective capacitance value of the storage capacitor;
wherein, during the operation of integration, the feedback switch element is configured to be driven into a closed state to selectively define a feedback path, and, outside of the operation of integration, is configured to be driven into an open state in order to interrupt the feedback path; and
wherein the coupling switch element is configured to selectively couple in parallel the test capacitor and the storage capacitor outside of the operation of integration in order to define jointly a discharge capacitance coupled to the discharge element.
16. The test circuit according to claim 9 , further comprising a reference-variation stage, configured to set the value of a comparison reference voltage supplied on a second input of the operational amplifier as a function of the effective resistance value of the discharge element.
17. A method for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal, the discharge element configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric, the method comprising:
biasing the floating node at a reading voltage;
detecting a biasing value of the reading voltage;
implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value; and
determining an effective resistance value of the discharge element as a function of the operation of integration.
18. The method according to claim 17 , wherein implementing the operation of integration comprises integrating the discharge current in the discharge element using an operational amplifier, having a first input terminal coupled to the floating node and coupled to receive the reading voltage, a second input terminal coupled to receive a comparison reference voltage having a value that is kept constant at the biasing value during the operation of integration, an output terminal configured to supply an output voltage, and a test capacitor selectively connected between the first input terminal and the output terminal during the operation of integration.
19. The method according to claim 18 , wherein the output voltage, during the operation of integration, has a voltage variation in a measurement time interval, and wherein the effective resistance value is a function according to the expression
R
L
′
~
V
x
(
t
0
)
Δ
V
out
·
Δ
T
C
T
where R L ′ is the effective resistance value, ΔVout is the voltage variation, ΔT is the measurement time interval, Vx(to) is the constant value of the comparison reference voltage, and C T is a capacitance value of the test capacitor.
20. The method according to claim 18 , wherein the detecting comprises iteratively varying the value of the comparison reference voltage supplied to the second input terminal of the operational amplifier, which operates as a comparator, wherein, upon switching of the output voltage of the operational amplifier, the value of the comparison reference voltage corresponds to a biasing value.
21. The method according to claim 17 , further comprising carrying out a shifting of the value of the reading voltage of the floating node from a negative value to a positive value, prior to detecting a biasing value of the reading voltage.
22. The method according to claim 21 , wherein carrying out the shifting comprises:
generating a shifting voltage; and
switching a voltage of the first biasing terminal and a second biasing terminal from a reference voltage to the shifting voltage, following upon biasing of the floating node at the reading voltage.