IP Library › Granted Patent US 10,281,775
Granted Patent B2
US 10,281,775 · App. 15/509,531 · Granted May 7, 2019

Display device

Inventors: Youhei Nakanishi (Sakai, JP); Masayuki Kanehiro (Sakai, JP)
Assignee: Sharp Kabushiki Kaisha
G02F1/1343G02F1/1333G02F1/134309G09F9/30G09G3/2003G09G3/3648G09G3/3677G02F1/133707G02F1/136286G02F2201/56G09G2300/0426G09G2310/0286
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,281,775
App. No.
15/509,531
Granted
May 7, 2019
Kind
B2
Abstract

A display device structure that, even if a plurality of non-display parts are formed in a pixel region, can display an image in the whole pixel region except the non-display parts is obtained. A display device 1 includes: a substrate ( 10 ) having a plurality of non-display parts in a pixel region (P); a plurality of source lines (SL 1 ), (SL 2 ), . . . , (SL m ); a plurality of gate lines (GL 1 ), (GL 2 ), . . . , (GL m ); a plurality of pixel electrodes; and a plurality of gate line drive circuits (GD k ) formed in the pixel region (P) and connected to each of the gate lines (GL 1 ), (GL 2 ), . . . , (GL m ), for controlling a potential of the gate line (GL k ). At least a source line interrupted by any of the plurality of non-display parts, among the source lines (SL 1 ), (SL 2 ), . . . , (SL m ) is supplied with a data signal from both ends thereof, and the source lines (SL 1 ), (SL 2 ), . . . , (SL m ) are each formed not to be interrupted by two or more of the plurality of non-display parts.

Claims (22)

1. A display device comprising:

a substrate including a plurality of non-display portions in a pixel region that displays an image;

a plurality of source lines each supplied with a data signal from outside;

a plurality of gate lines crossing the plurality of source lines;

a plurality of pixel electrodes provided at respective intersection points of the plurality of source lines and the plurality of gate lines; and

a plurality of gate line drive circuits provided in the pixel region and connected to each of the plurality of gate lines, that control a potential of the gate lines, wherein

at least a source line interrupted by any of the plurality of non-display portions, among the plurality of source lines, is supplied with the data signal from both ends thereof in two different directions, and

the plurality of source lines are each not interrupted by two or more of the plurality of non-display portions.

2. The display device according to claim 1 , wherein the plurality of non-display portions are each a hole.

3. The display device according to claim 1 , wherein the plurality of gate lines are each not interrupted by two or more of the plurality of non-display portions.

4. The display device according to claim 1 , wherein the substrate has a non-rectangular shape.

5. The display device according to claim 1 , further comprising:

a counter substrate facing the substrate; and

a liquid crystal layer sandwiched between the substrate and the counter substrate.

6. The display device according to claim 5 , wherein an angle between each of the plurality of gate lines and each of the plurality of source lines is 45 degrees to 89 degrees, and

a transparent electrode is provided on the gate line or the source line in the pixel region.

7. The display device according to claim 5 , wherein an angle between each of the plurality of gate lines and each of the plurality of source lines is 45 degrees, and

a drive mode of the display device is a vertical alignment mode.

8. The display device according to claim 1 , further comprising a plurality of signal lines to supply a control signal, wherein

the plurality of signal lines are arranged parallel to the source lines,

the plurality of gate line drive circuits are connected to each of the plurality of signal lines, and

the plurality of gate line drive circuits are arranged at approximately regular intervals along an extending direction of the gate lines.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2017
From: NAKANISHI, YOUHEI; KANEHIRO, MASAYUKI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 041500/0433 →
Priority Claims (1)
JP 2014-186744 · Sep 12, 2014 · national
Continuity (1)
Related Publication 20170276982A1 · Sep 28, 2017