Terahertz detector comprised of P-N junction diode

1. A method of forming a semiconductor detector structure, the method comprising:

forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an upper surface of an insulator layer of the SOI substrate, the insulator layer being formed on an upper surface of a carrier substrate of the SOI substrate;

removing the carrier substrate to thereby expose the insulator layer;

forming a first opening through the insulator layer to access a backside of a first doped region of the p-n junction diode, the first doped region underlying a second doped region of the p-n junction diode, the first doped region having a first conductivity type associated therewith and the second doped region having a second conductivity type associated therewith which is opposite in polarity to the first conductivity type;

forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region, the back contact being formed by epitaxially growing doped hydrogenated crystalline silicon in the first opening;

forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer comprising a first top contact providing electrical connection with the second doped region; and

forming an electrode of the p-n junction diode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the p-n junction diode.

2. The method of claim 1 , wherein the back contact is formed by epitaxially growing n-doped hydrogenated crystalline silicon with 5 to 40 atomic percent hydrogen using plasma-enhanced chemical vapor deposition at temperatures below 400 degrees Celsius.

3. The method of claim 1 , wherein the second doped region is formed by implanting a p-type impurity of a prescribed concentration level followed by annealing.

4. The method of claim 1 , wherein the second doped region is formed on the first doped region by epitaxially growing p + -doped hydrogenated crystalline silicon with 5 to 40 atomic percent hydrogen using plasma-enhanced chemical vapor deposition at temperatures below 400 degrees Celsius.

5. The method of claim 1 , further comprising forming shallow trench isolation (STI) structures in the active device layer proximate an upper surface of the SOI substrate and extending vertically through the active device layer to the insulator layer, the first and second doped regions being formed between two laterally adjacent STI structures.

6. The method of claim 5 , wherein the first opening is formed between adjacent STI structures, the first opening exposing a back surface of each of the adjacent STI structures, the method further comprising:

epitaxially growing n-doped hydrogenated silicon in the first opening; and

removing an amorphous portion of the hydrogenated silicon grown on the exposed back surfaces of the STI structures using selective etching, leaving behind an n + -doped hydrogenated crystalline silicon portion forming the back contact of the p-n junction diode.

7. The method of claim 1 , further comprising forming a dielectric layer on at least a portion of an upper surface of the active device layer of the SOI substrate.

8. The method of claim 7 , further comprising bonding a handle substrate to an upper surface of the dielectric layer.

9. The method of claim 7 , wherein the dielectric layer comprises an interlayer dielectric (ILD) layer.

10. A method of forming a semiconductor detector structure, the method comprising:

forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an upper surface of an insulator layer of the SOI substrate, the insulator layer being formed on an upper surface of a carrier substrate of the SOI substrate;

removing the carrier substrate to thereby expose the insulator layer;

forming a first opening through the insulator layer to access a backside of a first doped region of the p-n junction diode, the first doped region underlying a second doped region of the p-n junction diode, the first doped region having a first conductivity type associated therewith and the second doped region having a second conductivity type associated therewith which is opposite in polarity to the first conductivity type;

forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region;

forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer comprising a first top contact providing electrical connection with the second doped region;

forming an electrode of the p-n junction diode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the p-n junction diode;

forming shallow trench isolation (STI) structures in the active device layer proximate an upper surface of the SOI substrate and extending vertically through the active device layer to the insulator layer, the first and second doped regions being formed between two laterally adjacent STI structures; and

forming a conductive structure through at least a given one of the STI structures, the conductive structure providing electrical connection between a top contact formed on an upper surface of the SOI substrate and the electrode formed on the backside of the detector structure.

11. The method of claim 10 , wherein forming the conductive structure comprises:

forming a second opening through the insulator layer and through the given one of the STI structures to expose a back surface of the top contact; and

depositing conductive material in the first and second openings to form the electrode.

12. A method of forming a semiconductor detector structure, the method comprising:

forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an upper surface of an insulator layer of the SOI substrate, the insulator layer being formed on an upper surface of a carrier substrate of the SOI substrate;

removing the carrier substrate to thereby expose the insulator layer;

forming a first opening through the insulator layer to access a backside of a first doped region of the p-n junction diode, the first doped region underlying a second doped region of the p-n junction diode, the first doped region having a first conductivity type associated therewith and the second doped region having a second conductivity type associated therewith which is opposite in polarity to the first conductivity type;

forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region;

forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer comprising a first top contact providing electrical connection with the second doped region;

forming an electrode of the p-n junction diode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the p-n junction diode; and

forming a conductive structure through the SOI substrate, the conductive structure being electrically isolated from the second doped region and, in conjunction with the electrode, providing electrical connection between a second top contact formed on the upper surface of the SOI substrate and the first doped region.