Chip package structure and method for forming the same

1. A method for forming a chip package structure, comprising:

forming a first dielectric layer over a carrier substrate, wherein the first dielectric layer has first openings;

forming a first wiring layer over the first dielectric layer and in the first openings, wherein the first dielectric layer and the first wiring layer together form a redistribution structure, and the redistribution structure has a first surface and a second surface opposite to the first surface;

disposing a first chip and a first conductive bump over the first surface, wherein the first conductive bump is between the first chip and the redistribution structure;

forming a first molding layer over the first surface to surround the first chip and the first conductive bump;

removing the carrier substrate;

removing a first portion of the first dielectric layer to form a second opening after the removal of the carrier substrate;

forming a first conductive pad over the first dielectric layer and in the second opening to be electrically connected to the first wiring layer;

disposing a second chip and a second conductive bump over the second surface, wherein the second conductive bump is between the second chip and the redistribution structure; and

forming a second molding layer over the second surface to surround the second chip and the second conductive bump.

2. The method for forming the chip package structure as claimed in claim 1 , further comprising:

before the formation of the first molding layer, forming a first conductive pillar over the first surface, wherein the first conductive pillar is electrically connected to the first wiring layer, and the first molding layer further surrounds the first conductive pillar.

3. The method for forming the chip package structure as claimed in claim 2 , further comprising:

before the formation of the second molding layer, forming a second conductive pillar over the second surface, wherein the second molding layer further surrounds the second conductive pillar.

4. The method for forming the chip package structure as claimed in claim 3 , wherein the redistribution structure, the first chip, the first conductive bump, the first molding layer, the second chip, the second conductive bump, the second molding layer, the first conductive pillar, and the second conductive pillar together form a first chip package structure, and the method further comprises:

disposing the first chip package structure and a third conductive bump over a second chip package structure, wherein the third conductive bump is between the first conductive pillar and the second chip package structure and electrically connects the first conductive pillar to the second chip package structure.

5. The method for forming the chip package structure as claimed in claim 4 , further comprising:

disposing a third chip package structure and a fourth conductive bump over the first chip package structure, wherein the fourth conductive bump is between the third chip package structure and the second conductive pillar and electrically connects the third chip package structure to the second conductive pillar.

6. The method for forming the chip package structure as claimed in claim 5 , further comprising:

forming a third molding layer over the second chip package structure to surround the first chip package structure and the third chip package structure.

7. The method for forming the chip package structure as claimed in claim 1 , further comprising:

before the formation of the second molding layer, forming a conductive pillar over the second surface of the redistribution structure, wherein the second molding layer further surrounds the conductive pillar.

8. The method for forming the chip package structure as claimed in claim 1 , further comprising:

before the formation of the first dielectric layer, forming an adhesive layer on the carrier substrate, wherein the first dielectric layer is formed on the adhesive layer, the adhesive layer is in direct contact with the first dielectric layer, the carrier substrate, and the first wiring layer; and

during or after the removal of the carrier substrate, removing the adhesive layer.

9. The method for forming the chip package structure as claimed in claim 8 , wherein the adhesive layer is conformally formed on the carrier substrate, and the first dielectric layer is conformally formed on the adhesive layer.

10. The method for forming the chip package structure as claimed in claim 1 ,

wherein the second opening exposes a second portion of the first wiring layer and

the second conductive bump is bonded to the first conductive pad.

11. The method for forming the chip package structure as claimed in claim 10 , further comprising:

during the formation of the first conductive pad, forming a second conductive pad over the second surface, wherein the second conductive pad is electrically connected to the first wiring layer; and

forming a conductive pillar over the second conductive pad, wherein the second molding layer further surrounds the conductive pillar.

12. A method for forming a chip package structure, comprising:

forming a first redistribution structure over a carrier substrate;

disposing a first chip over the first redistribution structure over the carrier substrate after the formation of the first redistribution structure, wherein the first chip comprises a substrate and a conductive pad over the substrate;

forming a first molding layer over the first redistribution structure over the carrier substrate to surround the first chip;

forming a dielectric layer over the first molding layer and the first chip, wherein the dielectric layer has a first opening;

forming a wiring layer over the dielectric layer and in the first opening, the dielectric layer and the wiring layer together form a second redistribution structure, the second redistribution structure has a first surface and a second surface opposite to the first surface, the second surface faces the first chip, and the conductive pad is between the substrate and the second redistribution structure;

forming a first conductive pillar over the first surface, wherein the first conductive pillar is electrically connected to the wiring layer;

disposing a second chip and a first conductive bump over the first surface, wherein the first conductive bump is between the second chip and the second redistribution structure;

forming a second molding layer over the first surface to surround the first conductive pillar, the second chip, and the first conductive bump; and

removing the carrier substrate.

13. The method for forming the chip package structure as claimed in claim 12 , further comprising:

before the formation of the first molding layer, forming a second conductive pillar over the carrier substrate, wherein the first molding layer further surrounds the second conductive pillar, and the wiring layer is electrically connected to the second conductive pillar.

14. The method for forming the chip package structure as claimed in claim 12 , further comprising:

after the formation of the second molding layer, forming a third redistribution structure over the second molding layer and the first conductive pillar, wherein the third redistribution structure is electrically connected to the first conductive pillar.

15. A method for forming a chip package structure, comprising:

forming a dielectric layer over a carrier substrate, wherein the dielectric layer has openings;

forming a wiring layer over the dielectric layer and in the openings, wherein the dielectric layer and the wiring layer together form a redistribution structure, and the redistribution structure has a first surface and a second surface opposite to the first surface;

disposing a first chip and a first solder ball over the first surface, wherein the first solder ball is between the first chip and the redistribution structure;

forming a first molding layer over the first surface to surround the first chip and the first solder ball;

removing the carrier substrate to expose the wiring layer of the redistribution structure;

disposing a second chip and a second solder ball over the second surface, wherein the second solder ball is between the second chip and the redistribution structure and is between the second chip and the first chip; and

forming a second molding layer over the second surface to surround the second chip and the second solder ball.

16. The method for forming the chip package structure as claimed in claim 15 , wherein the first chip comprises a first substrate and a first conductive pillar over the first substrate, and the first conductive pillar partially penetrates into the first solder ball.

17. The method for forming the chip package structure as claimed in claim 15 , further comprising:

before the formation of the first molding layer, forming a first conductive pillar over the first surface, wherein the first conductive pillar is electrically connected to the wiring layer, the first molding layer further surrounds the first conductive pillar, and the first conductive pillar passes through the first molding layer.

18. The method for forming the chip package structure as claimed in claim 17 , wherein a first top surface of the first conductive pillar is substantially coplanar with a second top surface of the first molding layer.

19. The method for forming the chip package structure as claimed in claim 15 , further comprising:

after the removal of the carrier substrate and before the disposing of the second chip over the second surface, forming a first conductive pad that penetrates into the redistribution structure from the second surface of the redistribution structure.

20. The method for forming the chip package structure as claimed in claim 19 , further comprising:

during the formation of the first conductive pad, forming a second conductive pad over the second surface of the redistribution structure; and

forming a conductive pillar over the second conductive pad, wherein the conductive pillar is electrically connected to the wiring layer through the second conductive pad.