Integrated strained stacked nanosheet FET
Transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures. A gate is formed over and around the one or more semiconductor structures. A source and drain region is formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners.
1. A transistor, comprising:
a plurality of stress liners;
one or more semiconductor structures between the plurality of stress liners, wherein the stress liners provide a stress on the one or more semiconductor structures;
a gate formed over and around the one or more semiconductor structures; and
a source and drain region formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners.
2. The transistor of claim 1 , wherein the plurality of stress liners provide a compressive stress on the one or more semiconductor structures.
3. The transistor of claim 1 , wherein the plurality of stress liners provide a tensile stress on the one or more semiconductor structures.
4. The transistor of claim 1 , wherein the semiconductor structures are stacked nanowires.
5. The transistor of claim 1 , wherein the semiconductor structures are stacked nanosheets.
6. The transistor of claim 1 , wherein the stress liners comprise silicon nitride.
7. The transistor of claim 1 , further comprising at least one additional gate formed over and around the one or more semiconductor structures.
8. The transistor of claim 1 , further comprising a dielectric liner formed between the gate and the source and drain regions.
9. The transistor of claim 1 , wherein the gate is a gate stack comprising a gate conductor and a gate dielectric.