Vertical FET with strained channel
A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques.
1. An integrated circuit device comprising:
a substrate;
a hard mask;
a channel arranged in a vertical orientation to carry charge in a direction that is normal to an axial plane of the substrate, wherein the channel has an induced strain;
a first gate stack adjacent to the channel, wherein the first gate stack comprises a first high-k material, a first gate material, and a first work function metal between the first high-k material and the first gate material; and
a second gate stack over the channel.
2. The integrated circuit device of claim 1 wherein:
the channel comprises silicon germanium; wherein:
a lattice mismatch between silicon from a dummy fin and the silicon germanium of the channel causes the silicon germanium of the channel to have a compressive strain as the induced strain.
3. The integrated circuit device of claim 1 wherein:
the channel comprises a layer of silicon on silicon germanium; wherein:
a lattice mismatch between the silicon and the silicon germanium causes the silicon to have a tensile strain as the induced strain.
4. The integrated circuit device of claim 1 wherein:
the second gate stack comprises a second high-k material, a second gate material, and a second work function metal between the second high-k material and the second gate material.
5. The integrated circuit device of claim 1 wherein:
the first gate stack further comprises a bottom spacer between the first high-k material and the first work function metal.
6. The integrated circuit device of claim 1 wherein the first gate material is selected from a polysilicon or a tungsten-based material.
7. The integrated circuit device of claim 1 further comprising:
a bottom spacer adjacent to the substrate.