Circuits for correction of signals susceptible to baseline wander

1. A circuit for correction of a signal which is susceptible to baseline wander, the circuit comprising:

a front-end signal processing circuit, including a digital processing logic circuit, configured and arranged to process an input signal by mitigating signal artifacts;

a slicer circuit configured and arranged to sample the processed input signal and, therefrom, generate a symbol output derived from the sampled processed input signal;

a summing cross-over filter circuit configured and arranged between the front-end signal processing circuit and the slicer circuit to mitigate baseline wander in the symbol output; and

a decision feedback equalization (DFE) circuit coupled to the output of the slicer and the summing cross-over filter circuit to provide scaled feedback of previous symbols to the summing cross-over filter circuit.

2. The circuit of claim 1 , wherein the summing cross-over filter circuit, including a high-pass filter circuit and a low-pass filter circuit, is configured and arranged to remove and replace low-frequency content from the processed input signal with regenerated low-frequency content generated from a low-pass filtered version of the symbol output.

3. The circuit of claim 1 , wherein the summing cross-over filter circuit is configured and arranged to mitigate sensitivity of the circuit to low-frequency characteristics of transmission channels or transceiver front-ends.

4. The circuit of claim 1 , wherein the summing cross-over filter circuit includes:

a first circuit configured and arranged to perform a high-pass filtering process including receiving the processed input signal from the front-end signal processing circuit and providing a high-pass output that includes portions of the processed input signal having frequency content above a first threshold;

a second circuit configured and arranged to perform a low-pass filtering process including receiving the symbol output from the slicer circuit and, therefrom, providing a low-pass output that includes portions of the symbol output having frequency content below a second threshold; and

a summing circuit configured and arranged to output a sum of the high-pass output and the low-pass output to the slicer circuit.

5. The circuit of claim 4 , wherein corner frequencies of transfer functions of the first circuit and the second circuit track, such that the sum of the transfer functions approximate unity.

6. The circuit of claim 4 , wherein the DFE configured and arranged to provide feedback to the summing circuit derived from the symbol output, and including a gain compensation circuit configured and arranged in a pathway of the second circuit.

7. The circuit of claim 1 , wherein the front-end signal processing circuit configured and arranged to mitigate signal artifacts from the input signal includes mitigating signal echo and inter-symbol interference.

8. The circuit of claim 1 , wherein the front-end signal processing circuit configured and arranged to mitigate signal artifacts from the input signal includes performing normalization, echo-canceling and equalization on the input signal.

9. The circuit of claim 1 , wherein the front-end signal processing circuit includes an echo-cancelling circuit configured and arranged to mitigate signal echo from the input signal.

10. The circuit of claim 1 , wherein the front-end signal processing circuit includes an equalization circuit configured and arranged to mitigate inter-symbol interference from the input signal.

11. The circuit of claim 1 , further including an alternating current impedance circuit configured and arranged to receive the input signal conductively, capacitively, magnetically or acoustically.

12. The circuit of claim 1 , further including an analog-to-digital converter configured and arranged to digitize the input signal and output a sample, wherein the slicer circuit is configured and arranged to generate estimated values of symbols, and provide the symbol output indicative of the estimated values.

13. A circuit comprising:

a frontend signal processing circuit, including a digital processing logic circuit, configured and arranged to output a processed input signal by mitigating signal artifacts from an input signal;

a slicer circuit configured and arranged to sample the processed input signal and, therefrom, generate a symbol output derived from the sampled processed input signal;

a summing crossover filter circuit configured and arranged between the frontend signal processing circuit and the slicer circuit to mitigate baseline wander, the summing crossover filter circuit including:

a first circuit configured and arranged to receive the processed input signal from the frontend signal processing circuit and provide, to the slicer circuit, a highpass filtered version of the processed input signal having lowfrequency content attenuated;

a second circuit configured and arranged to receive the symbol output from the slicer circuit and provide a lowpass filtered version of the symbol output that is indicative of regenerated lowfrequency content to replace the attenuated low-frequency content; and

a decision feedback equalization (DFE) circuit coupled to the output of the slicer and the summing cross-over filter circuit to provide scaled feedback of previous symbols to the summing cross-over filter circuit.

14. The circuit of claim 13 , wherein the summing cross-over filter circuit is configured and arranged to compensate for baseline wander by replacing attenuated low-frequency content, as attenuated by the first circuit and a channel, with the regenerated low-frequency content derived from the low-pass filtered version of the symbol output, and while being insensitive to data path delays from the front-end signal processing circuit.

15. The circuit of claim 13 , wherein the summing cross-over filter circuit further includes a summing circuit configured and arranged between the first circuit and the second circuit, wherein the second circuit is configured and arranged to provide the low-pass filtered version of the symbol output, which is indicative of regenerated low-frequency content, to the summing circuit by attenuating frequency components above a threshold from the symbol output.

16. The circuit of claim 15 , wherein the summing circuit is configured and arranged to provide a sum of the high-pass filtered version of the processed input signal and the low-pass filtered version of the symbol output to the slicer circuit, wherein a sum of a transfer function of the high-pass filtering process and a transfer function of the low-pass filtering process approximate unity, such that the low-frequency content that is missing at the output of the first circuit, as attenuated by the first circuit, is replaced with the regenerated low-frequency content.

17. The circuit of claim 13 , wherein the first circuit is a high-pass filter and the second circuit is a low-pass filter, both the first and second circuits include first-order cross-over filters.

18. The circuit of claim 13 , wherein the first circuit and second circuit include cross-over filters of an order greater than one.

19. A method comprising:

providing a summing cross-over filter circuit configured and arranged between a front-end signal processing circuit, including a digital processing logic circuit, and a slicer circuit of a transceiver circuit;

mitigating signal artifacts from an input signal using the frontend signal processing circuit;

providing the input signal from the front-end signal processing circuit to the summing cross-over filter circuit;

mitigating baseline wander from the input signal using the summing crossover filter circuit and the slicer circuit including:

providing a highpass filtered version of the input signal, via a highpass filter circuit, to the slicer circuit;

generating, using the slicer circuit, a symbol ouput derived from the high-pass filtered version of the input signal;

providing a lowpass filtered version of the symbol output to summing circuitry;

replacing missing low-frequency content as attenuated by the high-pass path of the high-pass filter circuit with regenerated low-frequency content using the low-pass filtered version of the symbol ouput; and

providing a scaled feedback of previous symbols from an output of the slicer circuit using a decision feedback equalization (DFE) circuit coupled to the output of the slicer and the summing cross-over filter circuit.

20. The method of claim 19 , further including receiving the input signal via alternating current (AC)-coupled communication channels.