Stress isolation features for stacked dies
An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.
1. An integrated device package comprising:
a carrier formed of a semiconductor material;
an integrated device die mounted to the carrier;
a polymer buffer layer disposed between the integrated device die and the carrier, the polymer buffer layer comprising a pattern to reduce transmission of stresses between the carrier and the integrated device die, the pattern defined such that there is a gap between a portion of the integrated device die and a portion of the polymer buffer layer; and
an adhesive disposed between the integrated device die and the polymer buffer layer to directly mount the integrated device die to the polymer buffer layer with the adhesive.
2. The package of claim 1 , wherein the polymer buffer layer coats at least a portion of an exterior surface of the carrier.
3. The package of claim 1 , wherein the carrier comprises an additional integrated device die.
4. The package of claim 1 , wherein the pattern comprises a base region on the exterior surface of the carrier and one or more protrusions extending from the base region towards the integrated device die, the one or more protrusions covering less than all of an exterior surface of the integrated device die.
5. The package of claim 1 , wherein the polymer buffer layer underlies the entirety of the integrated device die.
6. The package of claim 1 , wherein the polymer buffer layer is patterned such that the gap is disposed between corner regions of the integrated device die and the polymer buffer layer.
7. The package of claim 1 , wherein the integrated device die comprises a microelectromechanical systems (MEMS) device die.
8. The package of claim 1 , wherein the pattern comprises one or more protrusions which support the integrated device die and one or more dam portions spaced from the protrusions to form a channel between the protrusions and the dam portions.
9. The package of claim 1 , further comprising a package substrate and a package lid mounted to the package substrate, wherein the carrier is mounted to the package substrate, and wherein the carrier and the integrated device die are disposed in a cavity defined by the package lid and the package substrate.
10. The package of claim 1 , wherein a thickness of the polymer buffer layer is in a range of 2 microns to 400 microns.
11. The package of claim 1 , further comprising a passivation layer between the exterior surface of the carrier and the polymer buffer layer, the polymer buffer layer deposited directly on the passivation layer.
12. The package of claim 1 , wherein the polymer buffer layer is spin coated on the exterior surface of the carrier.
13. The package of claim 1 , wherein the pattern is etched through at least a portion of the polymer buffer layer.
14. The package of claim 1 , wherein the polymer buffer layer contacts between 10% and 40% of an exterior surface of the integrated device die.
15. A method of manufacturing an integrated device package, the method comprising:
depositing a buffer layer on one of a carrier and an integrated device;
patterning the buffer layer through a portion of a thickness of the buffer layer to define a dual thickness for the buffer layer;
mounting the integrated device on the carrier such that the buffer layer is disposed between the carrier and a bottom surface of the integrated device; and
providing electrical communication to the integrated device by way of wire bonds, wherein no electrical connections are located between the bottom surface of the integrated device and a top surface of the carrier.
16. The method of claim 15 , wherein depositing the buffer layer comprises depositing the buffer layer on the carrier, the carrier comprising an additional integrated device.
17. The method of claim 15 , further comprising applying multiple spin coatings of the buffer layer on a first wafer.
18. The method of claim 15 , further comprising etching the buffer layer to define one or more pedestal portions and one or more dam portions spaced apart from the pedestal portions, the dam portions shorter than the pedestal portions.
19. An integrated device package comprising:
a carrier;
an integrated device die mounted to the carrier;
a polymer buffer layer disposed between a bottom surface of the integrated device die and a top surface of the carrier, the polymer buffer layer comprising a pattern to reduce transmission of stresses between the carrier and the integrated device die, the pattern defined such that there is a gap between a portion of the integrated device die and a portion of the polymer buffer layer, wherein electrical communication is provided to the integrated device die by way of wire bonds, and wherein no electrical connections are located between the bottom surface of the integrated device die and the top surface of the carrier; and
an adhesive disposed between the integrated device die and the polymer buffer layer to directly mount the integrated device die to the polymer buffer layer with the adhesive.
20. The integrated device package of claim 19 , wherein the polymer buffer layer is deposited on the top surface of the carrier, and wherein the carrier comprises another integrated device die.