Systems, apparatuses, and methods for lane-based strided gather
Embodiments of systems, apparatuses, and methods for lane-based strided gather are disclosed. In an embodiment, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for indices of addresses to memory, and a packed data destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from memory using the indices of the instruction, and for each type, store the extracted data elements in one or more lanes of a packed data destination register dedicated to that type, wherein relative data elements between types are strided data elements apart.
1. An apparatus comprising:
a decoder to decode an instruction, wherein the instruction to include fields for indices of addresses to memory, and a packed data destination register operand; and
execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from memory using the indices of the instruction, and for each type, store the extracted data elements in one or more lanes of a packed data destination register dedicated to that type, wherein relative data elements between types are strided data elements apart.
2. The apparatus of claim 1 , wherein the instruction to include an opcode indicating the defined number of types and stride value.
3. The apparatus of claim 2 , wherein the defined number of types are two, three, and four.
4. The apparatus of claim 1 , wherein the indices are stored in a packed data register.
5. The apparatus of claim 1 , wherein the instruction to indicate a size of the data elements.
6. The apparatus of claim 1 , wherein the instruction to include a writemask operand.
7. The apparatus of claim 1 , the execution circuitry to store extracted data element based on values of the writemask operand.
8. A method comprising:
decoding an instruction, wherein the instruction to include fields for indices of addresses to memory and a packed data destination register operand; and
executing the decoded instruction to extract data elements of a defined number of types from memory using the indices of the instruction, and for each type, store the extracted data elements in one or more lanes of a packed data destination register dedicated to that type, wherein relative data elements between types are strided data elements apart.
9. The method of claim 8 , wherein the instruction to include an opcode indicating the defined number of types and stride value.
10. The method of claim 9 , wherein the defined number of types are two, three, and four.
11. The method of claim 8 , wherein the indices are stored in a packed data register.
12. The method of claim 8 , wherein the instruction to indicate a size of the data elements.
13. The method of claim 8 , wherein the instruction to include a writemask operand.
14. The method of claim 8 , wherein the storing of extracted data element is based on values of the writemask operand.
15. A non-transitory machine-readable medium storing instructions which when executed to cause a processor to perform a method, the method comprising:
decoding an instruction, wherein the instruction to include fields for indices of addresses to memory and a packed data destination register operand; and
executing the decoded instruction to extract data elements of a defined number of types from memory using the indices of the instruction, and for each type, store the extracted data elements in one or more lanes of a packed data destination register dedicated to that type, wherein relative data elements between types are strided data elements apart.
16. The non-transitory machine-readable medium of claim 15 , wherein the instruction to include an opcode indicating the defined number of types and stride value.
17. The non-transitory machine-readable medium of claim 16 , wherein the defined number of types are two, three, and four.
18. The non-transitory machine-readable medium of claim 15 , wherein the indices are stored in a packed data register.
19. The non-transitory machine-readable medium of claim 15 , wherein the instruction to indicate a size of the data elements.
20. The non-transitory machine-readable medium of claim 15 , wherein the instruction to include a writemask operand.