IP Library Granted Patent US 10,289,950
Granted Patent B2
US 10,289,950 · App. 15/802,975 · Granted May 14, 2019

Monitoring potential of neuron circuits

Inventors: Kohji Hosokawa (Kawasaki, JP); Masatoshi Ishii (Kawasaki, JP); Atsuya Okazaki (Kawasaki, JP); Junka Okazawa (Kawasaki, JP); Takayuki Osogami (Tokyo, JP)
Assignee: International Business Machines Corporation
G06N3/063G06N3/049G06N3/0635
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Quick Facts
Patent No.
US 10,289,950
App. No.
15/802,975
Granted
May 14, 2019
Kind
B2
Abstract

A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Claims (16)

1. A method for monitoring a neuron potential in a neuromorphic electric system including a network of a plurality of layers, each layer including a plurality of input terminals and a plurality of output terminals, wherein

each of the plurality of layers is a network in which the plurality of input terminals and the plurality of output terminals are connected to each other via a plurality of resistor elements,

the plurality of input terminals include a plurality of general input terminals and one predetermined input terminal, the plurality of general input terminals receiving input from respective corresponding output terminals in a prior layer, the predetermined input terminal being unconnected to any one of the plurality of output terminals in the prior layer with a resistor element connected to the predetermined input terminal having a same resistance value as one of predetermined input terminals in each of the plurality of layers,

each of the plurality of output terminals is connected to a circuit that stores a charge obtained from input from the plurality of input terminals via the plurality of resistor elements, the circuit outputting a spike signal to a subsequent layer as an output from a layer the circuit belongs to, if a neuron potential of the circuit caused by the stored charge exceeds a predetermined threshold, and

the method comprises:

feeding test data to the neuromorphic electric system to cause the system to perform a normal operation; and

feeding a series of pulse signals from the predetermined input terminal to determine a number of pulse signals at a time when the circuit connected to each of the plurality of output terminals fires.

2. The method of claim 1 , further comprising changing a state of a switch in each of the plurality of layers to disable a leak function in at least one of the plurality of layers.

3. The method of claim 1 , further comprising changing a state of a switch in each of the plurality of layers to enable a leak function in at least one of the plurality of layers.

4. The method of claim 1 , further comprising setting a resistance value in the plurality of resistor elements.

5. The method of claim 1 , further comprising setting a resistance value in the plurality of resistor elements connected to the predetermined input terminal higher than resistance values in the plurality of resistor elements connected to the plurality of general input terminals.

6. The method of claim 1 , further comprising setting a resistance value in the plurality of resistor elements connected to the predetermined input terminal lower than resistance values in the plurality of resistor elements connected to the plurality of general input terminals.

7. The method of claim 1 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data.

8. The method of claim 1 , wherein the series of pulse signals occur at a fixed interval.

9. The method of claim 1 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data, with the resistance values greater than a fixed resistance value set in a resistor element connected to the predetermined input terminal.

10. The method of claim 1 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data, with the resistance values less than a fixed resistance value set in a resistor element connected to the predetermined input terminal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 054126/0693 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2017
From: HOSOKAWA, KOHJI; ISHII, MASATOSHI; OKAZAKI, ATSUYA; OKAZAWA, JUNKA; OSOGAMI, TAKAYUKI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044029/0577 →
Continuity (2)
Continuation 15411034 · Jan 20, 2017
Related Publication 20180211160A1 · Jul 26, 2018