Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.
1. A semiconductor structure, comprising:
a first dielectric layer;
a second dielectric layer over the first dielectric layer, the second dielectric layer and the first dielectric layer having different material compositions;
a third dielectric layer over the second dielectric layer, the third dielectric layer and the second dielectric layer having different material compositions;
a first conductive feature in the third dielectric layer, wherein the first conductive feature comprises a first metal line and a first via connected to the first metal line, the first metal line and the first via being in the third dielectric layer;
a first gap disposed around the first metal line and a first portion of the first via in the third dielectric layer; and
a second gap disposed around a second portion of the first via in the first dielectric layer, wherein a portion of the second dielectric layer is disposed between the first gap and the second gap.
2. The semiconductor structure of claim 1 , wherein the first gap has a width in a range from about 1 Å to about 100 Å.
3. The semiconductor structure of claim 1 , wherein the second dielectric layer has a thickness in a range from about 10 Å to about 300 Å.
4. The semiconductor structure of claim 1 , wherein the first dielectric layer extends completely under the first conductive feature.
5. The semiconductor structure of claim 1 , wherein the first conductive feature extends lower than a lower surface of the second dielectric layer.
6. The semiconductor structure of claim 1 , wherein the first via is a dummy via.
7. The semiconductor structure of claim 6 , further comprising:
a second conductive feature in the third dielectric layer, wherein the second conductive feature comprises a second metal line and a second via;
an underlying conductor in the first dielectric layer, wherein the second via extends through the second dielectric layer to the underlying conductor; and
a third gap interposed between the second conductive feature and the third dielectric layer.
8. The semiconductor structure of claim 7 , wherein the second dielectric layer is interposed between the third gap and the underlying conductor.
9. An interconnect structure, comprising:
a first dielectric layer;
a first etch stop layer (ESL) over the first dielectric layer;
a second dielectric layer over the first ESL;
a first conductive feature extending completely through the second dielectric layer and the first ESL into the first dielectric layer, the first conductive feature comprising a first line and a first via, the first via not being electrically interposed between the first line and any conductive feature in a lower dielectric layer; and
a first air gap disposed between a portion of the first conductive feature in the second dielectric layer and the second dielectric layer.
10. The interconnect structure of claim 9 , further comprising a second air gap disposed between a portion of the first conductive feature and the first dielectric layer.
11. The interconnect structure of claim 10 , wherein the first ESL is interposed between the first air gap and the second air gap.
12. The interconnect structure of claim 9 , wherein the first conductive feature extends lower than an upper surface of the first dielectric layer.
13. The interconnect structure of claim 9 , further comprising:
a second conductive feature extending completely through the second dielectric layer and the first ESL to a third conductive feature in the first dielectric layer; and
a second air gap disposed between the second conductive feature and the second dielectric layer.
14. The interconnect structure of claim 13 , wherein the first ESL is interposed between the second air gap and the third conductive feature.
15. An interconnect structure, comprising:
a first dielectric layer;
a second dielectric layer over the first dielectric layer;
a third dielectric layer over the second dielectric layer;
a first conductive feature extending through the third dielectric layer and the second dielectric layer, the first conductive feature extending only partially into the first dielectric layer;
a first void disposed between the first conductive feature and the third dielectric layer; and
a second void disposed between the first conductive feature and the first dielectric layer.
16. The interconnect structure of claim 15 , wherein the second dielectric layer is interposed between the first void and the second void.
17. The interconnect structure of claim 15 , wherein the first void is completely sealed off from the second void.
18. The interconnect structure of claim 15 , wherein the first dielectric layer extends completely under the second void.
19. The interconnect structure of claim 15 , wherein the first void extends from an upper surface of the third dielectric layer to the second dielectric layer.
20. The interconnect structure of claim 15 , wherein the first void has a width in a range from about 1 Å to about 100 Å.