IP Library Granted Patent US 10,290,600
Granted Patent B2
US 10,290,600 · App. 15/646,721 · Granted May 14, 2019

Dummy flip chip bumps for reducing stress

Inventors: Sheng-Yu Wu (Hsinchu, TW); Tin-Hao Kuo (Hsinchu, TW); Chita Chuang (Hsinchu, TW); Chen-Shien Chen (Zhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L24/17H01L21/563H01L23/3171H01L23/522H01L23/53238H01L23/562H01L23/585H01L24/06H01L24/11H01L24/14H01L24/81H01L24/13H01L24/16H01L2021/60255H01L2224/0345H01L2224/03912H01L2224/0401H01L2224/05005H01L2224/05008H01L2224/05022H01L2224/05027H01L2224/05166H01L2224/05181H01L2224/05186H01L2224/05541H01L2224/05569H01L2224/05572H01L2224/05582H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/05664H01L2224/05671H01L2224/05684H01L2224/06102H01L2224/1146H01L2224/1147H01L2224/11462H01L2224/11464H01L2224/13022H01L2224/13024H01L2224/13082H01L2224/13111H01L2224/13139H01L2224/13147H01L2224/13155H01L2224/13164H01L2224/141H01L2224/1403H01L2224/14051H01L2224/14152H01L2224/14179H01L2224/16237H01L2224/16238H01L2224/17104H01L2224/17517H01L2224/73204H01L2224/81007H01L2224/81101H01L2224/81191H01L2224/81815H01L2224/83104H01L2924/01029H01L2924/01047H01L2924/04941H01L2924/04953H01L2924/15787H01L2924/15788H01L2924/35H01L2924/3511
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Quick Facts
Patent No.
US 10,290,600
App. No.
15/646,721
Granted
May 14, 2019
Kind
B2
Abstract

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.

Claims (48)

1. A device comprising:

a substrate;

a metal pad over the substrate;

a passivation layer comprising a portion over the metal pad;

a post-passivation interconnect (PPI) electrically coupling to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer;

a polymer layer over the PPI;

a non-solder conductive feature comprising:

a first portion extending into the polymer layer to electrically couple to the metal pad; and

a second portion having a bottom surface contacting a top surface of the polymer layer; and

a dummy conductive feature having a bottom surface contacting the top surface of the polymer layer.

2. The device of claim 1 , wherein the dummy conductive feature comprises:

a non-solder conductive feature and a solder cap over the non-solder conductive feature.

3. The device of claim 1 further comprising a device over the non-solder conductive feature and the dummy conductive feature, wherein the device comprises a dielectric layer, and a bottom surface of the dielectric layer in the device is in contact with a top surface of the dummy conductive feature.

4. The device of claim 3 , wherein the dummy conductive feature comprises a solder region, and the bottom surface of the dielectric layer is in contact with the top surface of the dummy conductive feature.

5. The device of claim 4 , wherein the dummy conductive feature further comprises a non-solder portion underlying the solder region.

6. The device of claim 1 , wherein the polymer layer is a polyimide layer, and wherein the dummy conductive feature comprises a copper-containing material.

7. The device of claim 1 , wherein the dummy conductive feature is electrically insulated from all conductive features underlying the polymer layer.

8. A device comprising:

a first package component comprising:

a semiconductor substrate;

integrated circuit devices at a surface of the semiconductor substrate;

a surface dielectric layer at a surface of the first package component;

an electrical connector electrically coupling to the integrated circuit devices; and

a dummy conductive feature, wherein the dummy conductive feature is formed of a non-solder conductive material, with substantially an entirety of the dummy conductive feature being over the surface dielectric layer; and

a solder layer over and contacting the dummy conductive feature.

9. The device of claim 8 further comprising a second package component comprising a device die, an interposer, a package substrate, or a package, wherein the second package component is bonded to the first package component through solder, and the dummy conductive feature is electrically decoupled from the second package component.

10. The device of claim 9 , wherein the second package component comprises an additional surface dielectric layer, and the additional surface dielectric layer contacts the solder layer, and the additional surface dielectric layer electrically insulates the solder layer from features inside the second package component.

11. The device of claim 9 , wherein the dummy conductive feature is electrically coupled to a conductive feature in the second package component, and the dummy conductive feature and the conductive feature are in combination electrically floating.

12. The device of claim 8 , wherein the surface dielectric layer of the first package component comprises a polymer.

13. The device of claim 8 , wherein no via is formed in the surface dielectric layer to electrically couple to the dummy conductive feature.

14. The device of claim 8 , wherein the dummy conductive feature is adjacent to a corner of the first package component.

15. The device of claim 8 further comprising an underfill, wherein all sidewalls of the dummy conductive feature are in contact with the underfill.

16. A device comprising:

a first package component comprising:

a substrate;

a metal pad over the substrate;

a first dielectric layer over the metal pad;

an electrical connector extending into the first dielectric layer to electrically couple to the metal pad, wherein the electric connector comprises:

a first metal seed layer; and

a first metal pillar over the first metal seed layer; and

a dummy conductive feature over the first dielectric layer, wherein the dummy conductive feature comprises:

a second metal seed layer having a bottom surface contacting a top surface of the first dielectric layer, wherein the first metal seed layer and the second metal seed layer are formed of a same material; and

a second metal pillar over the second metal seed layer, wherein the first metal pillar and the second metal pillar are formed of a same non-solder material.

17. The device of claim 16 , wherein an entirety of a bottom surface of the second metal seed layer is in contact with the first dielectric layer.

18. The device of claim 16 , wherein the dummy conductive feature is in physical contact with the first dielectric layer.

19. The device of claim 16 further comprising a second package component bonded to the first package component, the second package component comprising:

a second dielectric layer at a surface of the second package component, wherein the dummy conductive feature is in contact with the second dielectric layer, and the dummy conductive feature is electrically insulated from conductive features in the second package component by the second dielectric layer.

20. The device of claim 19 , wherein the dummy conductive feature further comprises a solder cap, and the solder cap is in physical contact with the second dielectric layer.

Continuity (4)
Continuation 15054357 · Feb 26, 2016
Continuation 14491309 · Sep 19, 2014
Division 13211438 · Aug 17, 2011
Related Publication 20170309588A1 · Oct 26, 2017
Cited By (1)
US 12,278,208