Integrated circuit layout structure
An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.
1. An integrated circuit layout structure having dual-height standard cells, comprising:
at least a first standard cell having a first cell height, the first standard cell comprising one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell, the first doped region having a first conductivity type, the second doped regions having a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other, wherein a total area of the first doped region in the middle of the first standard cell is smaller than a total area of the second doped regions at the top side of the first standard cell and is smaller than a total area of the second doped regions at the bottom side of the first standard cell; and
at least a second standard cell having a second cell height, the second cell height being one half of the first cell height.
2. The integrated circuit layout structure having the dual-height standard cells according to claim 1 , wherein the second standard cell further comprises at least one or more third doped region comprising the first conductivity type and at least one or more fourth doped region comprising the second conductivity type.
3. The integrated circuit layout structure having the dual-height standard cells according to claim 1 , further comprising a first conductor extending across the middle of the first standard cell and a middle of the first doped region.
4. The integrated circuit layout structure having the dual-height standard cells according to claim 3 , further comprising a pair of second conductors respectively extending across a top and a bottom of the first standard cell, and one of the second conductors extending across a top or a bottom of the second standard cell.
5. The integrated circuit layout structure having the dual-height standard cells according to claim 4 , wherein the first conductor extends across the top or the bottom of the second standard cell opposite to the second conductor.
6. The integrated circuit layout structure having the dual-height standard cells according to claim 1 , wherein the first standard cell comprises pseudo n-channel metal-oxide-semiconductor (pseudo-NMOS) logic cell, or dynamic logic cell, or domino logic cell, or fully differential logic cell.
7. The integrated circuit layout structure having the dual-height standard cells according to claim 6 , wherein the first doped region comprises a PMOS transistor for Pull-up, and the second doped regions comprise NMOS Network for Logic operation.
8. An integrated circuit layout structure having dual-height standard cells, comprising:
at least a first standard cell having a first cell height, the first standard cell comprising one first doped region and a plurality of second doped regions, the first doped region having a first conductivity type, the second doped regions having a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other, wherein a total area of the first doped region in a middle of the first standard cell is smaller than a total area of the second doped regions at a top side of the first standard cell and is smaller than a total area of the second doped regions at a bottom side of the first standard cell;
at least a second standard cell having a second cell height, the second cell height being one half of the first cell height; and
a first conductor extending across a middle of the first standard cell.
9. The integrated circuit layout structure having the dual-height standard cells according to claim 8 , wherein the second standard cell further comprises at least one or more third doped region comprising the first conductivity type and at least one or more fourth doped region comprising the second conductivity type.
10. The integrated circuit layout structure having the dual-height standard cells according to claim 8 , wherein the first standard cell further comprises a plurality of first gate electrodes and the second standard cell further comprises a plurality of second gate electrodes.
11. The integrated circuit layout structure having the dual-height standard cells according to claim 10 , further comprising a plurality of gate connectors formed in between and electrically connecting the second gate electrodes, the second gate electrodes and the gate connectors comprise a same material formed in a same layer.
12. The integrated circuit layout structure having the dual-height standard cells according to claim 11 , wherein the first standard cell comprises no gate connector.
13. The integrated circuit layout structure having the dual-height standard cells according to claim 8 , further comprising a pair of second conductors extending across a top and a bottom of the first standard cell.
14. The integrated circuit layout structure having the dual-height standard cells according to claim 13 , wherein one of the second conductors extends across a top or a bottom of the second standard cell.
15. The integrated circuit layout structure having the dual-height standard cells according to claim 14 , wherein the first conductor extends across the top or the bottom of the second standard cell opposite to the second conductor.
16. The integrated circuit layout structure having the dual-height standard cells according to claim 8 , wherein the first standard cell comprises pseudo n-channel metal-oxide-semiconductor (pseudo-NMOS) logic cell, or dynamic logic cell, or domino logic cell, or fully differential logic cell.
17. The integrated circuit layout structure having the dual-height standard cells according to claim 16 , wherein the first doped region comprises a PMOS transistor for Pull-up, and the second doped regions comprise NMOS Network for Logic operation.