Manufacturing method of thin film transistor and manufacturing method of array substrate
The invention provides a manufacturing method of a thin film transistor and a manufacturing method of an array substrate. A photoresist is used to define a to-be-doped region of an amorphous silicon layer to thereby make a crystallization be occurred in a source contact region and a drain contact region. A crystallization direction is from the source contact region and the drain contact region towards a channel region, so that it can realize directional crystallization as far as possible, and therefore can improve crystallization efficiency and crystallization uniformity, reduce an influence of grain boundary applied to electron mobility and leakage current of the TFT and improve electrical characteristics of the TFT.
1. A manufacturing method of a thin film transistor, wherein the manufacturing method comprises:
providing a substrate;
sequentially forming an amorphous silicon layer and a photoresist layer on the substrate, using a mask to perform a patterning process to the photoresist layer to form spacedly-disposed photoresist patterns;
performing a doping process to the amorphous silicon layer being not covered by the photoresist patterns, wherein dopant ions in the doping process comprise boron ions;
stripping off the photoresist patterns and performing a rapid thermal annealing crystallization process to the amorphous silicon layer to thereby make a doping processed region of the amorphous silicon layer form a source contact region and a drain contact region and make a region covered by the photoresist patterns form a channel region;
forming a gate insulating layer on amorphous silicon layer after being performed with the rapid thermal annealing crystallization process; and
forming a gate pattern on the gate insulating layer, and the gate pattern being located between the source contact region and the drain contact region and correspondingly located above the channel region;
wherein the step of sequentially forming an amorphous silicon layer and a photoresist layer on the substrate comprises: sequentially forming a gate pattern and a gate insulting layer on the substrate; and sequentially forming the amorphous silicon layer and the photoresist layer on the gate insulting layer.
2. The manufacturing method according to claim 1 , wherein the manufacturing method further comprises:
forming an inter layer dielectric layer on the gate pattern;
forming contact holes penetrating through the inter layer dielectric layer and the gate insulting layer correspondingly above the source contact region and the drain contact region; and
forming a source pattern and a drain pattern on the interlayer dielectric layer correspondingly above the source contact region and the drain contact region respectively to thereby make the source pattern and the drain pattern respectively be electrically connected with the source contact region and the drain contact region by the contact holes.
3. A manufacturing method of a thin film transistor, wherein the manufacturing method comprises:
providing a substrate;
sequentially forming an amorphous silicon layer and a photoresist layer on the substrate, using a mask to perform a patterning process to the photoresist layer to form spacedly-disposed photoresist patterns;
performing a doping process to the amorphous silicon layer being not covered by the photoresist patterns; and
stripping off the photoresist patterns and performing a rapid thermal annealing crystallization process to the amorphous silicon layer to thereby make a doping processed region of the amorphous silicon layer form a source contact region and a drain contact region and make a region covered by the photoresist patterns form a channel region;
wherein the step of sequentially forming an amorphous silicon layer and a photoresist layer on the substrate comprises: sequentially forming a gate pattern and a gate insulting layer on the substrate; and sequentially forming the amorphous silicon layer and the photoresist layer on the gate insulting layer.
4. The manufacturing method according to claim 3 , wherein the manufacturing method further comprises:
forming a gate insulating layer on the amorphous silicon layer after being performed with the rapid thermal annealing crystallization process; and
forming a gate pattern on the gate insulating layer, and the gate pattern being located between the source contact region and the drain contact region and correspondingly located above the channel region.
5. The manufacturing method according to claim 4 , wherein the manufacturing method further comprises:
forming an interlayer dielectric layer on the gate pattern;
forming contact holes penetrating through the interlayer dielectric layer and the gate insulting layer correspondingly above the source contact region and the drain contact region; and
forming a source pattern and a drain pattern on the interlayer dielectric layer correspondingly above the source contact region and the drain contact region respectively to thereby make the source pattern and the drain pattern respectively be electrically connected with the source contact region and the drain contact region by the contact holes.
6. The manufacturing method according to claim 3 , wherein the manufacturing method further comprises:
forming an interlayer dielectric layer on the amorphous silicon layer after being performed with the rapid thermal annealing crystallization process;
forming contact holes penetrating through the interlayer dielectric layer correspondingly above the source contact region and the drain contact region; and
forming a source pattern and a drain pattern on the interlayer dielectric layer correspondingly above the source contact region and the drain contact region respectively to thereby make the source pattern and the drain pattern respectively be electrically connected with the source contact region and the drain contact region by the contact holes.
7. The manufacturing method according to claim 3 , wherein dopant ions in the doping process comprise boron ions.
8. A manufacturing method of an array substrate, wherein the manufacturing method comprises:
providing a substrate;
sequentially forming an amorphous silicon layer and a photoresist layer on the substrate, using a mask to perform a patterning process to the photoresist layer to form spacedly-disposed photoresist patterns;
performing a doping process to the amorphous silicon layer being not covered by the photoresist patterns;
stripping off the photoresist patterns and performing a rapid thermal annealing crystallization process to the amorphous silicon layer to thereby make a doping processed region of the amorphous silicon layer form a source contact region and a drain contact region and make a region covered by the photoresist patterns form a channel region;
forming an interlayer dielectric layer on the amorphous silicon layer after being performed with the rapid thermal annealing crystallization process;
forming first contact holes penetrating through the interlayer dielectric layer correspondingly above the source contact region and the drain contact region;
forming a source pattern and a drain pattern on the interlayer dielectric layer correspondingly above the source contact region and the drain contact region respectively to thereby make the source pattern and the drain pattern respectively be electrically connected with the source contact region and the drain contact region by the first contact holes;
forming a second contact hole for exposing the drain contact region correspondingly above the drain contact region;
forming a pixel electrode on the interlayer dielectric layer to thereby make the pixel electrode be electrically connected with the drain contact region by the second contact hole; and
wherein the step of sequentially forming an amorphous silicon layer and a photoresist layer on the substrate comprises: sequentially forming a gate pattern and a gate insulting layer on the substrate; and sequentially forming the amorphous silicon layer and the photoresist layer on the gate insulting layer.
9. The manufacturing method according to claim 8 , wherein
the step of forming an interlayer dielectric layer on the amorphous silicon layer after being performed with the rapid thermal annealing crystallization process comprises:
forming a gate insulating layer on the amorphous silicon layer after being performed with the rapid thermal annealing crystallization process;
forming a gate pattern on the gate insulating layer, and the gate pattern being located between the source contact region and the drain contact region and correspondingly located above the channel region; and
forming the inter layer dielectric layer on the gate pattern; and
the step of forming first contact holes penetrating through the interlayer dielectric layer correspondingly above the source contact region and the drain contact region comprises:
forming the first contact holes penetrating through the interlayer dielectric layer and the gate insulating layer correspondingly above the source contact region and the drain contact region.
10. The manufacturing method according to claim 8 , wherein dopant ions in the doping process comprise boron ions.