Power-gating control and method
A power-gating electronic system for synchronized power transitions, includes a power generation block including a plurality of cells, each cell including a cell enabling input; a circuit block including a plurality of circuits, each circuit including a circuit enabling input; and a power-gating controller including a plurality of gate signal outputs. In the power-gating electronic system, each gate signal output is coupled to one of the cell enabling inputs and one of the circuit enabling inputs.
1. A power-gating electronic system, comprising:
a power generation block including a plurality of cells, each cell including a cell enabling input;
a circuit block including a plurality of circuits, each circuit including a circuit enabling input; and
a power-gating controller including a plurality of gate signal outputs,
wherein each gate signal output is coupled to one of the cell enabling inputs and one of the circuit enabling inputs, and
the power-gating controller is configured to sequentially generate a plurality of gate signals based on a waiting time interval, each gate signal being provided on a distinct one of the plurality of gate signal outputs.
2. The power-gating electronic system of claim 1 , wherein each gate signal output is connected in series, first with the one circuit enabling input and second with the one cell enabling input.
3. The power-gating electronic system of claim 1 , wherein each gate signal output is connected in parallel with the one circuit enabling input and the one cell enabling input.
4. The power-gating electronic system of claim 3 , wherein a first electrical distance between a first one of the gate signal outputs and a first one of the cell enabling inputs that are connected, is substantially equal to a second electrical distance between the first gate signal output and a first one of the circuit enabling inputs that are connected.
5. The power-gating electronic system of claim 3 , wherein a first propagation time between a first one of the gate signal outputs and a first one of the cell enabling inputs that are connected, is substantially equal to a second propagation time between the first gate signal output and a first one of the circuit enabling inputs that are connected.
6. The power-gating electronic system of claim 5 , wherein a first signal propagation path between the first gate signal output and the first circuit enabling input and a second signal propagation path between the first gate signal output and the first cell enabling input include a buffered segment.
7. The power-gating electronic system of claim 1 , wherein the power-gating controller further comprises at least one of a current sensor, a capacitor sensor, and a temperature sensor.
8. The power-gating electronic system of claim 7 , wherein the power-gating controller calculates a waiting time interval based on at least one of measured current, measured capacitance, and measured temperature.
9. The power-gating electronic system of claim 1 , wherein the plurality of gate signals are generated and provided in groups.
10. The power-gating electronic system of claim 1 , wherein the waiting time interval is modified when a gate signal is generated.
11. The power-gating electronic system of claim 10 , wherein the waiting time interval increases when a gate signal is generated.
12. The power-gating electronic system of claim 1 , wherein each cell includes a cell power output and each circuit includes a circuit power input.
13. The power-gating electronic system of claim 12 , wherein each cell power output is connected directly to one of the circuit power inputs.
14. The power-gating electronic system of claim 1 , wherein each cell power output and each of circuit power input are connected to a voltage node.
15. A power-gating controller, comprising:
a memory device;
a control unit;
a plurality of gate signal outputs;
a power-gating detector in communication with the control unit; and
a demultiplexer coupled between the control unit and the plurality of gate signal outputs to route at least one of a plurality of gate signals to a selected one of the gate signal outputs,
wherein the memory device stores instructions that, when executed by the control unit, cause the control unit to:
determine a waiting time interval for gate signal output generation; and
sequentially generate the plurality of gate signals based on the determined waiting time interval, each gate signal being provided on a distinct one of the plurality of gate signal outputs.
16. The power-gating control of claim 15 , further comprising at least one of a current sensor, a capacitance sensor, and a temperature sensor; wherein the waiting time interval is determined based on at least one of a measured current, a measured capacitance, and a measured temperature.
17. The power-gating control of claim 15 wherein the memory device further stores instructions that cause the control unit to modify the waiting time interval when a gate-signal is generated.
18. A method for operating a power-gating electronic system, the method comprising:
determining a waiting time interval for gate signal generation;
determining a number of circuits to enter a powered down mode; and
sequentially generating a plurality of gate signals based on the determined waiting time interval, each gate signal being provided on a distinct one of a plurality of gate signal outputs of a power-gating controller,
wherein each gate signal output is coupled to one cell enabling input of a cell in a power generation block and one circuit enabling input of a circuit in a circuit block.