Pin-based noise characterization for silicon compiler

1. A method, comprising:

generating a set of circuit instances based upon an option set for a circuit;

for each I/O pin of the circuit, generating a family of equivalence classes from the set of circuit instances, where each circuit instance in an equivalence class in the family has a same leaf cell connected to each I/O pin;

for each I/O pin of the circuit, selecting one circuit instance from each equivalence class in the family associated with each I/O pin to generate a set of base circuit instances;

performing pin-based noise characterization of each base circuit instance; and

for each base circuit instance, using the pin-based noise characterization of each base circuit instance to noise characterize each circuit instance in the equivalence class from which each base circuit instance was selected.

2. The method as set forth in claim 1 , further comprising:

generating a noise database for the set of circuit instances based on the pin-based noise characterization of each base circuit instance.

3. The method as set forth in claim 1 , wherein the pin-based noise characterization of each base circuit instance is performed based upon a process, voltage, and temperature (PVT) corner.

4. The method as set forth in claim 3 , wherein the circuit is a memory circuit.

5. The method as set forth in claim 3 , further comprising:

fabricating a lithography mask based on at least one circuit instance in the set of circuit instances.

6. The method as set forth in claim 3 , wherein the pin-based noise characterization of each base circuit instance is based upon the Composite Current Source (CCS) noise model.

7. The method as set forth in claim 6 , further comprising:

for each I/O pin and each base circuit instance associated with each I/O pin:

partitioning a leaf cell instance in each base circuit instance that is connected to each I/O pin into a channel-connected block;

basing the pin-based noise characterization of each base circuit instance on a first stage in the channel-connected block for each base circuit instance if each I/O pin is an input pin; and

basing the pin-based noise characterization of each base circuit instance on a second stage in the channel-connected block for each base circuit instance if each I/O pin is an output pin.

8. A method, comprising:

generating a set of circuit instances based upon an option set for a circuit;

generating a set of base circuit instances as a proper subset of the set of circuit instances;

performing pin-based noise characterization of each base circuit instance;

generating a data structure including a noise database for the set of circuit instances based on the pin-based noise characterization of each base circuit instance in an equivalence class from which each base circuit instance was selected.

9. The method as set forth in claim 8 , further comprising:

for each base circuit instance, associating a subset of the set of circuit instances;

wherein generating the noise database for the set of circuit instances comprises using the pin-based noise characterization for each base circuit instance to generate pin-based noise characterization of its associated subset of the set of circuit instances.

10. The method as set forth in claim 8 , wherein generating the set of base circuit instances comprises:

for each I/O pin of the circuit, selecting circuit instances from the set of circuit instances such that no two selected circuit instances have a same leaf cell instance connected to each I/O pin;

wherein for all I/O pins all the selected circuit instances generate the set of base circuit instances.

11. The method as set forth in claim 10 , further comprising:

for each base circuit instance, associating a subset of the set of circuit instances by selecting those circuit instances in the set of circuit instances for which the I/O pin associated with each base circuit instance is connected to a same leaf cell;

wherein generating the noise database for the set of circuit instances comprises using the pin-based noise characterization for each base circuit instance to generate pin-based noise characterization of its associated subset of the set of circuit instances.

12. The method as set forth in claim 11 , wherein the circuit is a memory circuit.

13. The method as set forth in claim 11 , further comprising:

fabricating a lithography mask based on at least one circuit instance in the set of circuit instances.

14. The method as set forth in claim 11 , wherein the pin-based noise characterization is based upon the Composite Current Source (CCS) noise model.

15. An apparatus, comprising:

a memory to store instructions; and

a processor coupled to the memory that when executing the stored instructions:

generates a set of circuit instances based upon an option set for a circuit;

generates a set of base circuit instances as a proper subset of the set of circuit instances;

performs pin-based noise characterization of each base circuit instance; and

generates a noise database for the set of circuit instances based on the pin-based noise characterization of each base circuit instance.

16. The apparatus as set forth in claim 15 , the processor when further executing the stored instructions:

for each base circuit instance, associates a subset of the set of circuit instances;

wherein when generating the noise database for the set of circuit instances, uses the pin-based noise characterization for each base circuit instance to generate pin-based noise characterization of its associated subset of the set of circuit instances.

17. The apparatus as set forth in claim 15 , the processor when further generating the set of base circuit instances:

for each I/O pin of the circuit, selects circuit instances from the set of circuit instances such that no two selected circuit instances have a same leaf cell instance connected to each I/O pin;

wherein for all I/O pins, all the selected circuit instances are used by the processor to generate the set of base circuit instances.

18. The apparatus as set forth in claim 17 , the processor when further executing the stored instructions:

for each base circuit instance, associates a subset of the set of circuit instances by selecting those circuit instances in the set of circuit instances for which the I/O pin associated with each base circuit instance is connected to a same leaf cell;

wherein when generating the noise database for the set of circuit instances the processor uses the pin-based noise characterization for each base circuit instance to generate pin-based noise characterization of its associated subset of the set of circuit instances.

19. The apparatus as set forth in claim 18 , wherein the circuit is a memory circuit, the processor when further executing the stored instructions:

generates, based upon the noise database, a noise model inside a Liberty view of a given memory instance and for a given process, voltage, and temperature (PVT) corner.

20. The apparatus as set forth in claim 18 , wherein the pin-based noise characterization is based upon the Composite Current Source (CCS) noise model.