Semiconductor device and operating method thereof

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of cell strings;

an address decoder coupled to the memory cell array through word lines and configured for decoding an address for an operation on the memory cell array;

a read and write circuit configured for performing a read operation or a program operation on the memory cell array;

a control logic configured for controlling the address decoder and the read and write circuit to perform the read operation or the program operation on the memory cell array; and

an overdrive setting unit configured for determining an overdrive set parameter of an overdrive operation using an operation voltage applied to the word lines of the memory cell array,

wherein the control logic controls the overdrive operation using the operation voltage applied to the word lines on the basis of the overdrive set parameter, and

wherein the control logic controls the address decoder to apply the operation voltage having an overdrive voltage level greater than a target voltage level on the basis of the overdrive set parameter during an overdrive duration and to apply the operation voltage having the target voltage level after the overdrive duration.

2. The semiconductor memory device of claim 1 , wherein the overdrive setting unit comprises:

a temperature detection unit configured for detecting a temperature of the semiconductor memory device to generate temperature information;

a set parameter storage unit configured for storing a plurality of set parameters on the overdrive operation using the operation voltage; and

a set parameter determination unit configured for determining one of the plurality of set parameters stored in the set parameter storage unit as the overdrive set parameter of the operation voltage on the basis of the temperature information.

3. The semiconductor memory device of claim 2 , wherein the set parameter determination unit determines the overdrive voltage level of the operation voltage applied during the overdrive operation on the basis of the temperature information.

4. The semiconductor memory device of claim 3 , wherein the set parameter determination unit determines a voltage value having a lower level as the overdrive voltage level when the temperature information indicates higher temperature.

5. The semiconductor memory device of claim 2 , wherein the set parameter determination unit determines the overdrive duration for which the overdrive operation is performed on the basis of the temperature information.

6. The semiconductor memory device of claim 5 , wherein the set parameter determination unit determines a shorter time as the overdrive duration when the temperature information indicates higher temperature.

7. The semiconductor memory device of claim 2 , wherein the operation voltage includes at least one of a program verify voltage applied to the word lines during the program operation and a read voltage applied to the word lines during the read operation.

8. The semiconductor memory device of claim 1 , wherein the operation voltage is a program verify voltage applied to the word lines during the program operation, and

the overdrive setting unit comprises:

a program state detection unit configured for detecting a program state during the program operation;

a set parameter storage unit configured for storing a plurality of set parameters for the overdrive operation using the program verify voltage; and

a set parameter determination unit configured for determining one of the plurality of set parameters stored in the set parameter storage unit as the overdrive set parameter of the operation voltage on the basis of detected program state information.

9. The semiconductor memory device of claim 8 , wherein memory cells of the memory cell array are programmed to have one of an erase state and first to kth program states by the program operation of a selected word line, and

the set parameter determination unit changes an overdrive set parameter of a program verify voltage for each of (i+1)th to kth program states when a program operation for an ith program state, among the first to kth program states, is completed,

where k is a natural number of 2 or more and i is a natural number of 1 or more and less than k.

10. The semiconductor memory device of claim 9 , wherein the overdrive set parameter includes the overdrive voltage level of the operation voltage applied during the overdrive operation, and

the set parameter determination unit reduces the overdrive voltage level of the program verify voltage for each of the (i+1)th to kth program states when the program operation for the ith program state, among the first to kth program states, is completed.

11. The semiconductor memory device of claim 9 , wherein the overdrive set parameter includes the overdrive voltage level of the operation voltage applied during the overdrive operation, and

the set parameter determination unit increases the overdrive voltage level of the program verify voltage for each of the (i+1)th to kth program states when the program operation for the ith program state, among the first to kth program states, is completed.

12. The semiconductor memory device of claim 9 , wherein the overdrive set parameter includes the overdrive duration for which the overdrive operation is performed, and

the set parameter determination unit reduces the overdrive duration for which the overdrive operation using the program verify voltage for each of the (i+1)th to kth program states is performed when the program operation for the ith program state, among the first to kth program states, is completed.

13. The semiconductor memory device of claim 9 , wherein the overdrive set parameter includes the overdrive duration for which the overdrive operation is performed, and

the set parameter determination unit increases the overdrive duration for which the overdrive operation using the program verify voltage for each of the (i+1)th to kth program states is performed when the program operation for the ith program state, among the first to kth program states, is completed.

14. A method of operating a semiconductor memory device, the method comprising:

receiving an operation command for an operation of the semiconductor memory device;

detecting, by a temperature detection unit, a current temperature of the semiconductor memory device to generate temperature information;

determining, by a set parameter determination unit, an overdrive set parameter of an operation voltage related to the operation command on the basis of the temperature information, the operation voltage being to be applied to a word line of the semiconductor memory device;

applying, by a control logic, an operation voltage having an overdrive voltage level greater than a target voltage level on the basis of the overdrive set parameter to the word line; and

applying, by the control logic, the operation voltage having the target voltage level by reducing the overdrive voltage level to the word line.

15. The method of claim 14 , wherein the overdrive set parameter includes a voltage value determined by the overdrive voltage level, and

by the set parameter determination unit, the voltage value having a lower level is determined as the overdrive voltage level when the temperature information indicates higher temperature.

16. The method of claim 14 , wherein the overdrive set parameter includes an overdrive duration for which the overdrive operation is performed, and

by the set parameter determination unit, a shorter time is determined as the overdrive duration for which the temperature information indicates higher temperature.

17. A method of operating a semiconductor memory device, the method comprising:

receiving a program command for a program operation of the semiconductor memory device; and

performing, by a peripheral circuit and an overdriving setting unit, a program operation using a program verify voltage having an overdrive voltage level on the basis of program states of selected memory cells,

wherein memory cells of the semiconductor memory device are programmed to have one of an erase state and first to kth program states by the program operation, and

the performing of the program operation using the program verify voltage having the overdrive voltage level comprises:

performing, by the peripheral circuit, a program loop for an ith program state, among the first to kth program states, by using verify voltages having the overdrive voltage level;

determining, by a program state detection unit of the overdriving setting unit, whether a program operation for the ith program state is completed; and

changing, by a set parameter detection unit of the overdriving setting unit, an overdrive set parameter of a program verify voltage for each of (i+1)th to kth program states when the program operation for the ith program state is completed,

where k is a natural number of 2 or more and i is a natural number of 1 or more and less than k.

18. The method of claim 17 , further comprising performing, by the peripheral circuit, a program loop for the (i+1)th program state after changing the overdrive set parameter of the program verify voltage for each of the (i+1)th to kth program states after the program operation for the ith program state is completed.