IP Library › Granted Patent US 10,297,331

Granted Patent B2

US 10,297,331 · App. 15/333,723 · Granted May 21, 2019

Semiconductor device and electronic device

Inventor: Hiroyuki Miyake (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G11C19/28 G11C19/287 H01L27/124 H01L27/1225 H01L27/1251 H01L27/1255 H01L29/7869 H01L29/78648 G09G3/3677 G09G2310/0286

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Quick Facts

Patent No.: US 10,297,331
App. No.: 15/333,723
Granted: May 21, 2019
Kind: B2

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Abstract

A highly reliable semiconductor device is provided. A semiconductor device includes a shift register including a pulse output circuit formed using transistors having the same conductivity type, or the like. A transistor including a back gate is used as a transistor in which a potential difference between a source and a drain is not generated and positive stress is applied to a gate in a non-selection period of the pulse output circuit. In the non-selection period, stress applied to the transistors is reduced by interchanging the potentials of the gates and those of the back gates.

Claims (82)

1. A semiconductor device comprising:

first to twelfth transistors,

wherein the ninth to twelfth transistors each include a first gate and a second gate,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the ninth transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the second wiring,

wherein the first gate of the ninth transistor is electrically connected to the first gate of the tenth transistor,

wherein the second gate of the ninth transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the eleventh transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein the other of the source and the drain of the eleventh transistor is electrically connected to a gate of the fifth transistor,

wherein the first gate of the eleventh transistor is electrically connected to a fourth wiring,

wherein the second gate of the eleventh transistor is electrically connected to the second gate of the ninth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the tenth transistor,

wherein the second gate of the tenth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the twelfth transistor,

wherein a gate of the sixth transistor is electrically connected to the gate of the fifth transistor,

wherein the other of the source and the drain of the twelfth transistor is electrically connected to the second wiring,

wherein the first gate of the twelfth transistor is electrically connected to the first gate of the tenth transistor,

wherein the second gate of the twelfth transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the seventh transistor is electrically connected to the first gate of the tenth transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring,

wherein a gate of the seventh transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the third transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first gate of the tenth transistor, and

wherein a gate of the eighth transistor is electrically connected to the fourth wiring.

2. The semiconductor device according to claim 1 , further comprising a first capacitor,

wherein one of electrodes of the first capacitor is electrically connected to the gate of the sixth transistor, and

wherein the other of the electrodes of the first capacitor is electrically connected to one of the source and the drain of the twelfth transistor.

3. The semiconductor device according to claim 1 , further comprising a second capacitor,

wherein one of electrodes of the second capacitor is electrically connected to the other of the source and the drain of the third transistor, and

wherein the other of the electrodes of the second capacitor is electrically connected to the second wiring.

4. The semiconductor device according to claim 1 , further comprising a third capacitor,

wherein one of electrodes of the third capacitor is electrically connected to the first gate of the tenth transistor, and

wherein the other of the electrodes of the third capacitor is electrically connected to the second wiring.

5. The semiconductor device according to claim 1 , wherein one of the source and the drain of the sixth transistor is electrically connected to a wiring through which a first clock signal is supplied.

6. The semiconductor device according to claim 1 , wherein a gate of the first transistor is electrically connected to a wiring through which a reset signal is supplied.

7. The semiconductor device according to claim 1 , wherein the gate of the second transistor is electrically connected to a wiring through which a start signal is supplied.

8. The semiconductor device according to claim 1 , wherein a gate of the third transistor is electrically connected to a wiring through which a second clock signal is supplied.

9. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the fifth transistor is configured to output a signal.

10. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the sixth transistor is configured to output a signal.

11. The semiconductor device according to claim 1 , wherein the first to twelfth transistors have the same conductivity type.

12. The semiconductor device according to claim 1 , wherein the first to twelfth transistors each comprise an oxide semiconductor layer where a channel is formed.

13. An electronic device comprising:

the semiconductor device according to claim 1 ; and

a touch sensor, an antenna, a battery, a housing, a speaker, a microphone, or an operation switch.

14. A semiconductor device comprising:

a pulse output circuit comprising:

a first transistor comprising a source, a drain, and a gate;

a second transistor comprising a source, a drain, a first gate, and a second gate;

a third transistor comprising a source, a drain, a first gate, and a second gate;

a fourth transistor comprising a source, a drain, and a gate;

a fifth transistor comprising a source, a drain, and a gate;

a sixth transistor comprising a source, a drain, and a gate; and a seventh transistor comprising a source, a drain and a gate;

wherein one of the source and the drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,

wherein the gate of the first transistor is electrically connected to a second wiring through the source and the drain of the fifth transistor and to a third wiring through the source and the drain of the third transistor,

wherein one of the first gate and the second gate of the second transistor and one of the first gate and the second gate of the third transistor are each electrically connected to the second wiring through the source and the drain of the fourth transistor,

wherein the other of the first gate and the second gate of the second transistor and the other of the first gate and the second gate of the third transistor are each electrically connected to a fourth wiring,

wherein the gate of the fourth transistor is electrically connected to a fifth wiring,

wherein the gate of the sixth transistor is electrically connected to the fourth wiring, and

wherein the one of the first gate and the second gate of the second transistor and the one of the first gate and the second gate of the third transistor are each electrically connected to the third wiring through the source and the drain of the sixth transistor wherein the gate of the seventh transistor is electrically connected to the gate of the fifth transistor, and wherein the one of the first gate and the second gate of the second transistor and the one of the first gate and the second gate of the third transistor are each electrically connected to the third wiring through the source and the drain of the fourth transistor and the source and the drain of the seventh transistor.

15. The semiconductor device according to claim 14 ,

wherein the fourth wiring is configured to be supplied with a first signal, and

wherein the fifth wiring is configured to be supplied with a second signal that is opposite to the first signal.

16. The semiconductor device according to claim 14 , comprising a capacitor comprising a first electrode and a second electrode,

wherein the first electrode of the capacitor is electrically connected to the gate of the first transistor, and

wherein the second electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor and the one of the source and the drain of the second transistor.

17. The semiconductor device according to claim 14 ,

wherein each of the second transistor and the third transistor comprises:

a semiconductor layer between the first gate and the second gate;

a first gate insulating layer between the first gate and the semiconductor layer; and

a second gate insulating layer between the second gate and the semiconductor layer, and

wherein the semiconductor layer is positioned between the first gate insulating layer and the second gate insulating layer.

18. The semiconductor device according to claim 17 , wherein the semiconductor layer comprises an oxide semiconductor.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2016

From: MIYAKE, HIROYUKI

To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Reel/Frame 040121/0258 →

Priority Claims (1)

JP 2015-214320 · Oct 30, 2015 · national

Continuity (1)

Related Publication 20170125122A1 · May 4, 2017

Cited By (8)

US 12,212,317 US 12,243,459 US 12,394,364 US 12,431,207 US 12,476,636 US 12,482,413 US 12,575,132 US 12,706,013