IP Library › Granted Patent US 10,297,747
Granted Patent B2
US 10,297,747 · App. 15/958,444 · Granted May 21, 2019

Apparatus and methods for integrating magnetoresistive devices

Inventors: Sarin A. Deshpande (Chandler, AZ); Sanjeev Aggarwal (Scottsdale, AZ); Moazzem Hossain (Chandler, AZ)
Assignee: Everpsin Technologies, Inc.
H01L43/12G11C11/161H01L21/768H01L27/222H01L43/02H01L43/08
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Quick Facts
Patent No.
US 10,297,747
App. No.
15/958,444
Granted
May 21, 2019
Kind
B2
Abstract

The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.

Claims (39)

1. A method of fabricating an integrated circuit device having a magnetoresistive device, comprising:

forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region;

depositing a first dielectric material over the magnetoresistive device, wherein the first dielectric material is a low-k or an ultra low-k dielectric material;

depositing a second dielectric material over the first dielectric material, wherein the second dielectric material is a conventional dielectric material;

polishing a surface of the second dielectric material;

forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and

depositing an electrically conductive material in the first cavity to form a via.

2. The method of claim 1 , wherein a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material.

3. The method of claim 1 , wherein the polishing is halted before the first dielectric material is exposed.

4. The method of claim 1 , wherein the polishing is halted when the first dielectric material is exposed.

5. The method of claim 1 , further comprising:

polishing a portion of the first dielectric material above the magnetoresistive device after polishing the surface of the second dielectric material.

6. The method of claim 1 , further comprising:

depositing a third dielectric material after forming the via;

polishing a surface of the third dielectric material;

forming a second cavity through the polished surface of the third dielectric material to expose a surface of the via; and

depositing a second electrically conductive material in the second cavity.

7. The method of claim 6 , wherein a dielectric constant of the third dielectric material is lower than the dielectric constant of the second dielectric material.

8. The method of claim 6 , wherein the third dielectric material is a low-k or an ultra low-k dielectric material.

9. The method of claim 6 , wherein a dielectric constant of the second dielectric material is higher than a dielectric constant of each of the first dielectric material and the third dielectric material.

10. A method of fabricating an integrated circuit device having a magnetoresistive device, comprising:

forming a magnetoresistive device, wherein the magnetoresistive device includes a plurality of magnetic regions separated by an intermediate region;

depositing a first dielectric material over the magnetoresistive device, wherein the first dielectric material is a low-k or an ultra low-k dielectric material;

polishing a surface of the first dielectric material;

depositing a second dielectric material over the polished surface of the first dielectric material, wherein the second dielectric material is a conventional dielectric material;

forming a first cavity through a surface of the second dielectric material; and

depositing an electrically conductive material in the first cavity.

11. The method of claim 10 , wherein a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material.

12. The method of claim 10 , wherein the polishing is halted before the magnetoresistive device is exposed.

13. The method of claim 10 , wherein forming the first cavity comprises etching through the second dielectric material and the first dielectric material by adjusting etchant chemistry.

14. The method of claim 10 , further comprising:

depositing a third dielectric material after forming the via;

polishing a surface of the third dielectric material;

forming a second cavity through the polished surface of the third dielectric material to expose a surface of the via; and

depositing an electrically conductive material in the second cavity.

15. The method of claim 14 , wherein a dielectric constant of the third dielectric material is lower than the dielectric constant of the second dielectric material.

16. The method of claim 14 , wherein the third dielectric material is a low-k or an ultra low-k dielectric material.

17. The method of claim 14 , wherein the second dielectric material is a conventional dielectric material.

18. The method of claim 14 , wherein a dielectric constant of the second dielectric material is higher than a dielectric constant of each of the first dielectric material and the third dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2018
From: DESHPANDE, SARIN A.; AGGARWAL, SANJEEV; HOSSAIN, MOAZZEM
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 045795/0445 →
Continuity (2)
Provisional Application 62488233 · Apr 21, 2017
Related Publication 20180309051A1 · Oct 25, 2018