Double compression avoidance
The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.
1. A control circuit for controlling skew and minimizing double cycle compression between at least three clocks and their associated clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals, the control circuit comprising:
multiple programmable delay elements arranged within a signal flow before a respective clock domain;
a skew detector arrangement for detecting skew between at least two pairs of clock signals, and a control circuit for adjusting delays caused by the programmable delay elements, wherein the control circuit comprises one or more deferral elements and wherein the one or more deferral elements is deferring decrementing value stored in one or more counters by one or more clock cycles; and
wherein the control circuit executes a de-skewing operation, the de-skewing operation comprising:
determining an order of occurrence of edges of the clock signals;
selecting one of the programmable delay elements based on the determined order; and
adjusting the delay by the one or more deferral elements caused by the selected programmable delay element.
2. The skew control circuit of claim 1 , wherein the control circuit iteratively executes the de-skewing operation for different cycles of the clock signals.
3. The skew control circuit of claim 1 , wherein the control circuit comprises at least one counter for holding a control value for controlling the delay caused by a programmable delay element and wherein adjusting the delay comprises incrementing or decrementing the counter.
4. The skew control circuit of claim 1 , further comprising:
selecting a first programmable delay element associated with a first clock signal corresponding to the last occurring edge.
5. The skew control circuit of claim 4 , wherein the de-skewing operation comprises deferring adjusting the delay of a second programmable delay element associated with a second clock signal having an earlier occurring edge.
6. The skew control circuit of claim 5 , wherein the de-skewing operation comprises deferring decreasing the delay of a third programmable delay element.
7. The skew control circuit of claim 1 , wherein determining the order of occurrences of the edges is based on determining the order of occurrences of the edges of pairs of signals.