Efficient random number generation for update events in multi-bank conditional branch predictor

1. A branch predictor, comprising:

a plurality of memory banks having entries that hold prediction information for predicting a direction of branch instructions fetched and executed by a processor that comprises the branch predictor;

a counter of events that occur in the processor; hardware logic which is configured for performing an arithmetic and/or logical operation on predetermined bits of the counter to generate a random value; and wherein

in response to the processor determining the direction of a branch instruction predicted by the branch predictor, the branch predictor is configured for using the random value generated by the hardware logic to make a decision about updating the memory banks;

a branch history pattern that specifies a history of directions of branch instructions encountered by the processor; and wherein the hardware logic, in addition to performing the arithmetic or logical operation on predetermined bits of the count, performs the arithmetic and/or logical operation also on predetermined bits of the branch history pattern to generate the random value;

wherein the arithmetic or logical operation comprises a Boolean exclusive-OR (XOR) operation of a first portion of bits of the count with a second portion of bits of the count;

wherein the event counted comprises a retire of an instruction by the processor.

2. The branch predictor of claim 1 , further comprising: wherein the event counted comprises a cycle of a clock of an external bus to which the processor is coupled.

3. The branch predictor of claim 1 , further comprising: wherein the event counted comprises a cycle of a core clock of the processor.

4. The branch predictor of claim 1 , further comprising: wherein the random value is from a set of possible values; wherein when the direction predicted by the branch predictor matches the correct direction, the branch predictor is configured to allocate, a new entry in one or more of the plurality of memory banks if the random value is one of a predetermined subset of the set of possible values and otherwise does not to allocate a new entry in one or more of the plurality of memory banks.

5. The branch predictor of claim 1 , further comprising: wherein the random value is from a set of possible values; wherein when the direction predicted by the branch predictor does not match the correct direction, the branch predictor is configured to allocate a new entry in more than one of the plurality of memory banks if the random value is one of a predetermined subset of the set of possible values and otherwise to allocate a new entry in one of the plurality of memory banks.

6. The branch predictor of claim 1 , further comprising:

wherein the random value is from a set of possible values;

wherein each bank of the plurality of memory banks is configured to receive an index computed using a different length of a branch history pattern, and each bank of the plurality of memory banks has a number, and the bank numbers increase sequentially from shortest length to longest length; and

wherein each entry in the plurality of memory banks includes an indicator that indicates whether the entry has tended to be useful in predicting the direction of branch instructions;

wherein when allocating an entry in the plurality of banks in response to the processor determining the correct direction of a branch instruction having a direction was predicted by a first bank of the plurality of memory banks having a bank number X, the branch predictor begins searching for a non-useful entry to allocate at bank numbered X+1 if the random value is one of a predetermined subset of the set of possible values and otherwise begins searching for a non-useful entry to allocate at bank numbered X+2.

7. The branch predictor of claim 1 , further comprising: wherein each entry in the plurality of memory banks includes an indicator that indicates whether the entry has tended to be useful in predicting the direction of branch instructions; a counter incremented by a number of banks whose indicator indicates its entry has tended to be useful and decremented by a number of banks whose indicator indicates its entry has tended not to be useful; and wherein the branch predictor probabilistically decrements the indicators when the counter has a value greater than or equal to the random value.

8. A method of operating a branch predictor that has a plurality of memory banks having entries that hold prediction information used to predict a direction of branch instructions fetched and executed by a processor that comprises the branch predictor, the method comprising:

maintaining a count of events that occur in the processor;

performing an arithmetic and/or logical operation on predetermined bits of the count to generate a random value; and

in response to the processor determining the direction of a branch instruction predicted by the branch predictor, using the generated random value to make a decision about updating the memory banks;

maintaining a branch history pattern that specifies a history of directions of branch instructions encountered by the processor; and in addition to performing the arithmetic or logical operation on predetermined bits of the count, performing the arithmetic or logical operation also on predetermined bits of the branch history pattern to generate the random value;

wherein the arithmetic and/or logical operation comprises a Boolean exclusive-OR (XOR) operation of a first portion of bits of the count with a second portion of bits of the count;

wherein the event counted comprises a retire of an instruction by the processor.

9. The method of claim 8 , further comprising: wherein the event counted comprises a cycle of a clock of an external bus to which the processor is coupled.

10. The method of claim 8 , further comprising: wherein the event counted comprises a cycle of a core clock of the processor.

11. The method of claim 8 , further comprising: wherein the random value is from a set of possible values; when the direction predicted by the branch predictor matches the correct direction, allocating a new entry in one or more of the plurality of memory banks if the random value is one of a predetermined subset of the set of possible values and otherwise not allocating a new entry in one or more of the plurality of memory banks.

12. The method of claim 8 , further comprising:

wherein the random value is from a set of possible values; when the direction predicted by the branch predictor does not match the correct direction, allocating a new entry in more than one of the plurality of memory banks if the random value is one of a predetermined subset of the set of possible values and otherwise allocating a new entry in one of the plurality of memory banks.

13. The method of claim 8 , further comprising:

wherein the random value is from a set of possible values; wherein each bank of the plurality of memory banks receives an index computed using a different length of a branch history pattern, and each bank of the plurality of memory banks has a number, and the bank numbers increase sequentially from shortest length to longest length; and

wherein each entry in the plurality of memory banks includes an indicator that indicates whether the entry has tended to be useful in predicting the direction of branch instructions; when allocating an entry in the plurality of banks in response to the processor determining the correct direction of a branch instruction whose direction was predicted by a first bank of the plurality of memory banks having a bank number X, beginning to search for a non-useful entry to allocate at bank numbered X+1 if the random value is one of a predetermined subset of the set of possible values and otherwise beginning to search for a non-useful entry to allocate at bank numbered X+2.

14. The method of claim 8 , further comprising:

wherein each entry in the plurality of memory banks includes an indicator that indicates whether the entry has tended to be useful in predicting the direction of branch instructions;

incrementing a counter by a number of banks whose indicator indicates its entry has tended to be useful and decrementing the counter by a number of banks whose indicator indicates its entry has tended not to be useful; and

probabilistically decrementing the indicators when the counter has a value greater than or equal to the random value.

15. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a branch predictor, the computer usable program code comprising:

first program code for specifying a plurality of memory banks having entries that hold prediction information used to predict a direction of branch instructions fetched and executed by a processor that comprises the branch predictor;

second program code for specifying a count of events that occur in the processor;

third program code for specifying hardware logic that performs an arithmetic and/or logical operation on predetermined bits of the count to generate a random value; and

wherein in response to the processor determining a correct direction of a branch instruction predicted by the branch predictor, the branch predictor uses the random value generated by the hardware logic to make a decision about updating the memory banks;

a branch history pattern that specifies a history of directions of branch instructions encountered by the processor; and wherein the hardware logic, in addition to performing the arithmetic or logical operation on predetermined bits of the count, performs the arithmetic and/or logical operation also on predetermined bits of the branch history pattern to generate the random value;

wherein the arithmetic or logical operation comprises a Boolean exclusive-OR (XOR) operation of a first portion of bits of the count with a second portion of bits of the count;

wherein the event counted comprises a retire of an instruction by the processor.