IP Library › Granted Patent US 10,303,595
Granted Patent B2
US 10,303,595 · App. 15/641,028 · Granted May 28, 2019

Apparatus and method for dynamically managing memory

Inventor: Ik Soon Kim (Daejeon, KR)
Assignee: Electronics and Telecommunications Research Institute
G06F12/023G06F12/0207G06F12/0292G06F12/0653G06F2212/1044
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Quick Facts
Patent No.
US 10,303,595
App. No.
15/641,028
Granted
May 28, 2019
Kind
B2
Abstract

The present invention relates to a dynamic memory management method which includes generating an N-dimensional memory address space in which coordinates are in a range of N natural numbers, the sum of which is the number of bits; and mapping a predetermined linear memory address region to an address region in the N-dimensional memory address space.

Claims (20)

1. A dynamic memory management method comprising:

generating an N-dimensional memory address space in a predetermined memory; and

mapping a predetermined linear memory address region to an address region in the N-dimensional memory address space according to a memory allocation request, the mapping of the predetermined linear memory address region including:

converting addresses of the predetermined linear memory address region to spatial memory addresses by mapping a coordinate value consisting of N natural numbers, which are multiplied to become the linear memory address, to a spatial memory address in an N-dimensional space, and

mapping the predetermined linear memory address region to a space region in a range of the converted spatial memory addresses.

2. The dynamic memory management method of claim 1 , wherein the generating of the N-dimensional memory address space includes generating an N-dimensional memory address space in which coordinates are in a range of N natural numbers, the sum of which is the number of bits of a linear memory.

3. The dynamic memory management method of claim 1 , wherein the mapping of the predetermined linear memory address region includes:

converting a minimum value address and a maximum value address of the predetermined linear memory address region to spatial memory addresses; and

mapping the predetermined linear memory address region to a space region ranging from the spatial memory address converted from the minimum value address to the spatial memory address converted from the maximum value address.

4. The dynamic memory management method of claim 1 , further comprising managing regions adjacent to an allocated spatial memory address region by combining the regions into free spaces when memory deallocation is performed.

5. A dynamic memory management apparatus comprising:

a memory address space generator configured to generate an N-dimensional memory address space in a predetermined memory; and

a memory allocator configured to map a predetermined linear memory address region to an address region in the N-dimensional memory address space according to a memory allocation request, the memory allocator including:

an address converter configured to convert addresses of the predetermined linear memory address region to spatial memory addresses by mapping coordinate values consisting of N natural numbers, which are multiplied to become the linear memory address, to a spatial memory address in an N-dimensional space; and

a region mapper configured to map the predetermined linear memory address region to a space region in a range of the converted spatial memory addresses.

6. The dynamic memory management apparatus of claim 5 , wherein the memory address space generator generates the N-dimensional memory address space in which coordinates are in a range of N natural numbers, the sum of which is the number of bits of a linear memory.

7. The dynamic memory management apparatus of claim 5 , wherein the memory allocator includes:

an address converter configured to convert a minimum value address and a maximum value address of the predetermined linear memory address region to spatial memory addresses; and

a region mapper configured to map the predetermined linear memory address region to a space region ranging from the spatial memory address converted from the minimum value address to the spatial memory address converted from the maximum value address.

8. The dynamic memory management apparatus of claim 5 , further comprising a memory deallocator configured to manage regions adjacent to an allocated spatial memory address region by combining the regions into free spaces when memory deallocation is performed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2017
From: KIM, IK SOON
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 042935/0393 →
Priority Claims (1)
KR 10-2016-0084828 · Jul 5, 2016 · national
Continuity (1)
Related Publication 20180011786A1 · Jan 11, 2018