Intelligent data prefetching using address delta prediction

1. A method, comprising:

prior to determining that a first load instruction specifying a first virtual address misses in a data cache:

determining that a prior instance of an instruction specifying a second virtual address misses in the data cache,

determining that the miss of the prior instance of the instruction specifying the second virtual address resolves,

storing an indication of the prior instance of the instruction specifying the second virtual address in a miss tracking table (MTT), and

determining, based on respective age values stored in the MTT, that a prior instance of the instruction specifying the first virtual address is the next oldest instruction that missed in the data cache relative to the prior instance of the instruction specifying the second virtual address;

determining that the first load instruction specifying the first virtual address misses in the data cache;

receiving, from an address delta predictor (ADP), a delta value based on a program counter value of the first load instruction;

determining that a confidence value received from the ADP based on the program counter value of the first load instruction exceeds a predefined threshold;

computing the second virtual address based on the delta value and the first virtual address; and

prefetching, from a main memory to the data cache, data associated with the second virtual address prior to a second load instruction specifying the second virtual address missing in the data cache.

2. The method of claim 1 , further comprising:

computing the delta value based on a difference of the first and second virtual addresses of the prior instances of the instructions specifying the first and second virtual addresses, respectively; and

storing an indication of: (i) the program counter value, (ii) the computed delta value, and (iii) the confidence value in the ADP, wherein the program counter value of the first load instruction and the prior instance of the instruction specifying the first virtual address.

3. The method of claim 1 , further comprising prior to storing the indication of the prior instance of the instruction specifying the second virtual address in the MTT:

determining that the prior instance of the instruction specifying the first virtual address missed in the data cache;

determining that the miss of the prior instance of the instruction specifying the first virtual address resolves; and

storing an indication of the prior instance of the instruction specifying the first virtual address in the MTT.

4. The method of claim 3 , wherein the MTT comprises a plurality of entries, wherein each entry of the MTT is configured to store: (i) a program counter value, (ii) a virtual address, and (iii) an age value of a respective load instruction specifying a respective virtual address that misses in the data cache.

5. The method of claim 1 , further comprising:

upon determining that the prefetching is served by the data cache, decrementing the confidence value in the ADP; and

upon determining that the prefetching is served by the main memory, incrementing the confidence value in the ADP.

6. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform an operation comprising:

prior to determining that a first load instruction specifying a first virtual address misses in a data cache:

determining that a prior instance of an instruction specifying a second virtual address misses in the data cache,

determining that the miss of the prior instance of the instruction specifying the second virtual address resolves,

storing an indication of the prior instance of the instruction specifying the second virtual address in a miss tracking table (MTT), and

determining, based on respective age values stored in the MTT, that a prior instance of the instruction specifying the first virtual address is the next oldest instruction that missed in the data cache relative to the prior instance of the instruction specifying the second virtual address;

determining that the first load instruction specifying the first virtual address misses in the data cache;

receiving, from an address delta predictor (ADP), a delta value based on a program counter value of the first load instruction;

determining that a confidence value received from the ADP based on the program counter value of the first load instruction exceeds a predefined threshold;

computing the second virtual address based on the delta value and the first virtual address; and

prefetching, from a main memory to the data cache, data associated with the second virtual address prior to a second load instruction specifying the second virtual address missing in the data cache.

7. The non-transitory computer-readable medium of claim 6 , the operation further comprising:

computing the delta value based on a difference of the first and second virtual addresses of the prior instances of the instructions specifying the first and second virtual addresses, respectively; and

storing an indication of: (i) the program counter value, (ii) the computed delta value, and (iii) the confidence value in the ADP, wherein the program counter value of the first load instruction and the prior instance of the instruction specifying the first virtual address.

8. The non-transitory computer-readable medium of claim 6 , the operation further comprising prior to storing the indication of the prior instance of the instruction specifying the second virtual address in the MTT:

determining that the prior instance of the instruction specifying the first virtual address missed in the data cache;

determining that the miss of the prior instance of the instruction specifying the first virtual address resolves; and

storing an indication of the prior instance of the instruction specifying the first virtual address in the MTT.

9. The non-transitory computer-readable medium of claim 8 , wherein the MTT comprises a plurality of entries, wherein each entry of the MTT is configured to store: (i) a program counter value, (ii) a virtual address, and (iii) an age value of a respective load instruction specifying a respective virtual address that misses in the data cache.

10. The non-transitory computer-readable medium of claim 6 , the operation further comprising:

upon determining that the prefetching is served by the data cache, decrementing the confidence value in the ADP; and

upon determining that the prefetching is served by the main memory, incrementing the confidence value in the ADP.

11. An apparatus, comprising:

an address delta predictor (ADP);

a data cache;

a main memory; and

logic configured to perform an operation comprising:

prior to determining that a first load instruction specifying a first virtual address misses in a data cache:

determining that a prior instance of an instruction specifying a second virtual address misses in the data cache,

determining that the miss of the prior instance of the instruction specifying the second virtual address resolves,

storing an indication of the prior instance of the instruction specifying the second virtual address in a miss tracking table (MTT), and

determining, based on respective age values stored in the MTT, that a prior instance of the instruction specifying the first virtual address is the next oldest instruction that missed in the data cache relative to the prior instance of the instruction specifying the second virtual address;

determining that first load instruction specifying the first virtual address misses in the data cache;

receiving, from the ADP, a delta value based on a program counter value of the first load instruction;

determining that a confidence value received from the ADP based on the program counter value of the first load instruction exceeds a predefined threshold;

computing the second virtual address based on the delta value and the first virtual address; and

prefetching, from the main memory to the data cache, data associated with the second virtual address prior to a second load instruction specifying the second virtual address missing in the data cache.

12. The apparatus of claim 11 , the operation further comprising:

computing the delta value based on a difference of the first and second virtual addresses of the prior instances of the instructions specifying the first and second virtual addresses, respectively; and

storing an indication of: (i) the program counter value, (ii) the computed delta value, and (iii) the confidence value in the ADP, wherein the program counter value of the first load instruction and the prior instance of the instruction specifying the first virtual address.

13. The apparatus of claim 11 , the operation further comprising prior to storing the indication of the prior instance of the instruction specifying the second virtual address in the MTT:

determining that the prior instance of the instruction specifying the first virtual address missed in the data cache;

determining that the miss of the prior instance of the instruction specifying the first virtual address resolves; and

storing an indication of the prior instance of the instruction specifying the first virtual address in the MTT.

14. The apparatus of claim 13 , wherein the MTT comprises a plurality of entries, wherein each entry of the MTT is configured to store: (i) a program counter value, (ii) a virtual address, and (iii) an age value of a respective load instruction specifying a respective virtual address that misses in the data cache.

15. The apparatus of claim 11 , the operation further comprising:

upon determining that the prefetching is served by the data cache, decrementing the confidence value in the ADP; and

upon determining that the prefetching is served by the main memory, incrementing the confidence value in the ADP.

16. An apparatus, comprising:

an address delta predictor (ADP);

a miss tracking table;

a data cache;

a main memory;

means for prior to determining that a first load instruction specifying a first virtual address misses in a data cache:

determining that a prior instance of an instruction specifying a second virtual address misses in the data cache,

determining that the miss of the prior instance of the instruction specifying the second virtual address resolves,

storing an indication of the prior instance of the instruction specifying the second virtual address in a miss tracking table (MTT), and

determining, based on respective age values stored in the MTT, that a prior instance of the instruction specifying the first virtual address is the next oldest instruction that missed in the data cache relative to the prior instance of the instruction specifying the second virtual address;

means for determining that the first load instruction specifying the first virtual address misses in the data cache;

means for receiving, from the ADP, a delta value based on a program counter value of the first load instruction;

means for determining, prior to computing the second virtual address, that a confidence value received from the ADP based on the program counter value of the first load instruction exceeds a predefined threshold;

means for computing a second virtual address based on the delta value and the first virtual address; and

means for prefetching, from the main memory to the data cache, data associated with the second virtual address prior to a second load instruction specifying the second virtual address missing in the data cache.

17. The apparatus of claim 16 , further comprising:

means for computing the delta value based on a difference of the first and second virtual addresses of the prior instances of the instructions specifying the first and second virtual addresses, respectively; and

means for storing an indication of: (i) the program counter value, (ii) the computed delta value, and (iii) the confidence value in the ADP, wherein the program counter value of the first load instruction and the prior instance of the instruction specifying the first virtual address.

18. The apparatus of claim 16 , further comprising prior to storing the indication of the prior instance of the instruction specifying the second virtual address in the MTT:

means for determining that the prior instance of the instruction specifying the first virtual address missed in the data cache;

means for determining that the miss of the prior instance of the instruction specifying the first virtual address resolves; and

means for storing an indication of the prior instance of the instruction specifying the first virtual address in the MTT.

19. The apparatus of claim 18 , wherein the MTT comprises a plurality of entries, wherein each entry of the MTT comprises means for storing: (i) a program counter value, (ii) a virtual address, and (iii) an age value of a respective load instruction specifying a respective virtual address that misses in the data cache.

20. The apparatus of claim 16 , further comprising:

means for decrementing the confidence value in the ADP upon determining that the prefetching is served by the data cache; and

means for incrementing the confidence value in the ADP upon determining that the prefetching is served by the main memory.