Power and performance-efficient cache design for a memory encryption engine

1. An electronic device, comprising:

a memory encryption engine (MEE) coupleable to one or more processor cores, and further comprising:

a MEE cache configured to store a plurality of MEE cache lines, each MEE cache line comprising a plurality of cryptographic metadata blocks, where each cryptographic metadata block is associated with each of a plurality of encrypted data lines stored in a memory, and each MEE cache line includes a bit vector mapped to the plurality of cryptographic metadata blocks, where a set bit in the bit vector indicates that the associated cryptographic metadata block has been accessed by the one or more processor cores; and

MEE circuitry configured to:

select a replacement candidate from the plurality of MEE cache lines for eviction from the MEE cache based on a number of accessed cryptographic metadata blocks in the replacement candidate as indicated by the associated bit vector.

2. The electronic device of claim 1 , wherein, in selecting the replacement candidate, the MEE circuitry is further configured to:

determine a number of set bits in each bit vector of the plurality of MEE cache lines;

search for a MEE cache line having a bit vector with all bits set; and

in response to finding a MEE cache line with a bit vector having all bits set, select the MEE cache line with the bit vector having all bits set as the replacement candidate.

3. The electronic device of claim 2 , wherein, in response to not finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select as the replacement candidate, a MEE cache line from the plurality of MEE cache lines having the greatest number of bits set in the associated bit vector.

4. The electronic device of claim 2 , wherein, in response to not finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select as the replacement candidate, a least recently used (LRU) MEE cache line from the plurality of MEE cache lines.

5. The electronic device of claim 2 , wherein the MEE cache further comprises:

a recently evicted address (REA) buffer having a plurality of entries for storing a plurality of memory addresses;

a miss counter associated with each of the plurality of entries of the REA buffer;

and, in response to finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select the MEE cache line with the bit vector having all bits set as the replacement candidate.

6. The electronic device of claim 5 , wherein, in response to not finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select as the replacement candidate, a MEE cache line from the plurality of MEE cache lines having the greatest number of bits set in the associated bit vector;

evict the replacement candidate from the MEE cache;

enter a memory address for the replacement candidate into the REA buffer;

perform a lookup of the REA buffer for a hit on the memory address of the replacement candidate whenever a MEE cache lookup returns a miss;

increment the miss counter each time the lookup of the REA buffer returns a hit; and

select as a replacement candidate, on a next eviction from the MEE cache, a least recently used (LRU) MEE cache line if the miss counter is greater than or equal to a threshold number of returned misses.

7. The electronic device of claim 1 , wherein the MEE circuitry is further configured to:

determine a number of set bits in each bit vector of the plurality of MEE cache lines;

search for a MEE cache line having a bit vector with all bits set;

invalidate the MEE cache line; and

set a MEE cache way holding invalidated MEE cache line to an empty way.

8. The electronic device of claim 1 , wherein the number of accessed cryptographic metadata blocks in the replacement candidate is all of the cryptographic metadata blocks in the replacement candidate.

9. The electronic device of claim 1 , wherein the number of accessed cryptographic metadata blocks in the replacement candidate is a greatest number of the cryptographic metadata blocks in a MEE cache line of the plurality of MEE cache lines.

10. A computing system, comprising:

one or more processor cores;

a memory controller coupled to the one or more processor cores;

a memory encryption engine (MEE) coupled to the one or more processor cores and to the memory controller, and further comprising:

a MEE cache configured to store a plurality of MEE cache lines, each MEE cache line comprising a plurality of cryptographic metadata blocks, where each cryptographic metadata block is associated with each of a plurality of encrypted data lines stored in a memory, and each MEE cache line includes a bit vector mapped to the plurality of cryptographic metadata blocks, where a set bit in the bit vector indicates that the associated cryptographic metadata block has been accessed by the one or more processors cores; and

MEE circuitry configured to:

select a replacement candidate from the plurality of MEE cache lines for eviction from the MEE cache based on a number of accessed cryptographic metadata blocks in the replacement candidate as indicated by the associated bit vector.

11. The computing system of claim 10 , wherein, in selecting the replacement candidate, the MEE circuitry is further configured to:

determine a number of set bits in each bit vector of the plurality of MEE cache lines;

search for a MEE cache line having a bit vector with all bits set; and

in response to finding a MEE cache line with a bit vector having all bits set, select the MEE cache line with the bit vector having all bits set as the replacement candidate.

12. The computing system of claim 11 , wherein, in response to not finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select as the replacement candidate, a MEE cache line from the plurality of MEE cache lines having the greatest number of bits set in the associated bit vector.

13. The computing system of claim 11 , wherein, in response to not finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select as the replacement candidate, a least recently used (LRU) MEE cache line from the plurality of MEE cache lines.

14. The computing system of claim 11 , wherein the MEE cache further comprises:

a recently evicted address (REA) buffer having a plurality of entries for storing a plurality of memory addresses;

a miss counter associated with each of the plurality of entries of the REA buffer;

and, in response to finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select the MEE cache line with the bit vector having all bits set as the replacement candidate.

15. The computing system of claim 14 , wherein, in response to not finding a MEE cache line with a bit vector having all bits set, the MEE circuitry is further configured to:

select as the replacement candidate, a MEE cache line from the plurality of MEE cache lines having the greatest number of bits set in the associated bit vector;

evict the replacement candidate from the MEE cache;

enter a memory address for the replacement candidate into the REA buffer;

perform a lookup of the REA buffer for a hit on the memory address of the replacement candidate whenever a MEE cache lookup returns a miss;

increment the miss counter each time the lookup of the REA buffer returns a hit; and

select as a replacement candidate, on a next eviction from the MEE cache, a least recently used (LRU) MEE cache line if the miss counter is greater than or equal to a threshold number of returned misses.

16. The computing system of claim 10 , wherein the MEE circuitry is further configured to:

determine a number of set bits in each bit vector of the plurality of MEE cache lines;

search for a MEE cache line having a bit vector with all bits set;

invalidate the MEE cache line; and

set a MEE cache way holding invalidated MEE cache line to an empty way.

17. The computing system of claim 10 , wherein the number of accessed cryptographic metadata blocks in the replacement candidate is all of the cryptographic metadata blocks in the replacement candidate.

18. The computing system of claim 10 , wherein the number of accessed cryptographic metadata blocks in the replacement candidate is a greatest number of the cryptographic metadata blocks in a MEE cache line of the plurality of MEE cache lines.

19. A computer-implemented method, comprising:

receiving, in a memory encryption engine (MEE), a MEE cache line for entry into a MEE cache of the MEE, where the MEE cache does not include an empty way, and the MEE cache line comprises a plurality of cryptographic metadata blocks, where each cryptographic metadata block is associated with each of a plurality of encrypted data lines stored in a memory, and the MEE cache line includes a bit vector mapped to the plurality of cryptographic metadata blocks, where a set bit in the bit vector indicates that the associated cryptographic metadata block has been accessed by one or more processors; and

selecting a replacement candidate for eviction from the MEE cache, using the MEE, from a plurality of MEE cache lines in the MEE cache, where the selection is based on a number of accessed cryptographic metadata blocks in the replacement candidate as indicated by the associated bit vector.

20. The computer-implemented method of claim 19 , when selecting the replacement candidate, further comprises:

determining a number of set bits in each bit vector of the plurality of MEE cache lines;

searching for a MEE cache line having a bit vector with all bits set;

and, in response to finding a MEE cache line with a bit vector having all bits set, selecting the MEE cache line with the bit vector having all bits set as the replacement candidate.

21. The computer-implemented method of claim 20 , when not finding a MEE cache line with a bit vector having all bits set, further comprises:

selecting as the replacement candidate, a MEE cache line from the plurality of MEE cache lines having the greatest number of bits set in the associated bit vector.

22. The computer-implemented method of claim 20 , when not finding a MEE cache line with a bit vector having all bits set, further comprises:

selecting as the replacement candidate, a least recently used (LRU) MEE cache line from the plurality of MEE cache lines.

23. The computer-implemented method of claim 20 , when not finding a MEE cache line with a bit vector having all bits set, further comprises:

selecting as the replacement candidate, a MEE cache line from the plurality of MEE cache lines having the greatest number of bits set in the associated bit vector;

evicting the replacement candidate from the MEE cache;

entering a memory address of the replacement candidate to a recently evicted address (REA) buffer;

incrementing a miss counter associated with the memory address of the replacement candidate for each MEE cache miss that is a REA buffer hit for the memory address of the replacement candidate; and

selecting a least recently used (LRU) MEE cache line for a subsequent replacement candidate if the miss counter exceeds a threshold.

24. The computer-implemented method of claim 19 , further comprising:

determining a number of set bits in each bit vector of the plurality of MEE cache lines;

searching for a MEE cache line having a bit vector with all bits set;

invalidating the MEE cache line; and

setting a MEE cache way holding invalidated MEE cache line to an empty cache way.

25. The computer-implemented method of claim 19 , wherein the number of accessed cryptographic metadata blocks in the replacement candidate is all of the cryptographic metadata blocks in the replacement candidate.

26. The computer-implemented method of claim 19 , wherein the number of accessed cryptographic metadata blocks in the replacement candidate is a greatest number of the cryptographic metadata blocks in a MEE cache line of the plurality of MEE cache lines.