Hybrid integration of photodetector array with digital front end
The present disclosure relates to optical receiver systems. An example optical receiver system includes a first substrate with a plurality of photodetectors and a bias circuit. The bias circuit is electrically coupled to each photodetector of the plurality of photodetectors. The bias circuit is configured to provide a bias voltage to each photodetector. The optical receiver system also includes a plurality of capacitors. Each capacitor of the plurality of capacitors is electrically-coupled to a respective photodetector of the plurality of photodetectors. The optical receiver system also includes a second substrate with a read-out circuit having a plurality of channels. Each channel of the plurality of channels is capacitively-coupled to a respective photodetector via the respective capacitor.
1. A system comprising:
a first substrate comprising:
a plurality of photodetectors; and
a bias circuit, wherein the bias circuit is electrically coupled to each photodetector of the plurality of photodetectors, wherein the bias circuit is configured to provide a bias voltage to each photodetector; and
a second substrate comprising:
a silicon-on-insulator (SOI) material;
a plurality of capacitors, wherein:
each capacitor of the plurality of capacitors is electrically coupled to a respective photodetector of the plurality of photodetectors; and
each capacitor comprises two metal layers separated by a buried oxide layer of the SOI material; and
a read-out circuit having a plurality of channels, wherein each channel of the plurality of channels is capacitively coupled to a respective photodetector of the plurality of photodetectors via a respective capacitor of the plurality of capacitors.
2. The system of claim 1 , wherein the read-out circuit comprises a complementary metal-oxide-semiconductor (CMOS) digital read-out integrated circuit (ROIC).
3. The system of claim 2 , wherein the complementary metal-oxide-semiconductor (CMOS) digital read-out integrated circuit (ROIC) includes design features less than 32 nanometers in size.
4. The system of claim 1 , wherein the plurality of photodetectors comprises a plurality of single photon avalanche photodetectors (SPADs).
5. The system of claim 1 , wherein the bias circuit comprises a passive quenching circuit, wherein the bias voltage is at least 70 volts.
6. The system of claim 1 , wherein each channel comprises a respective CMOS transistor, wherein each capacitor of the plurality of capacitors is electrically coupled to an input gate terminal of the respective CMOS transistor.
7. The system of claim 6 , wherein a respective capacitance value of each capacitor of the plurality of capacitors is selected based on at least the bias voltage and a desired input voltage at the respective input gate terminal.
8. The system of claim 7 , wherein the desired input voltage is less than 5.5 volts.
9. The system of claim 1 , wherein the plurality of capacitors is disposed on the first substrate.
10. The system of claim 1 , wherein the system is at least a portion of an optical receiver of a Light Detection and Ranging (LIDAR) system.
11. A method of manufacture comprising:
providing a first substrate, wherein the first substrate comprises:
a plurality of photodetectors; and
a bias circuit, wherein the bias circuit is electrically coupled to each photodetector of the plurality of photodetectors, wherein the bias circuit is configured to provide a bias voltage to each photodetector;
providing a second substrate comprising a read-out circuit having a plurality of channels wherein the second substrate comprises a silicon-on-insulator (SOI) material;
forming a plurality of capacitors on the second substrate, wherein:
each capacitor of the plurality of capacitors is electrically coupled to a respective photodetector of the plurality of photodetectors; and
each capacitor comprises two metal layers separated by a buried oxide layer of the SOI material; and
each channel of the plurality of channels is capacitively coupled to a respective photodetector of the plurality of photodetectors via the respective capacitor of the plurality of capacitors; and
coupling the first substrate and the second substrate.
12. The method of claim 11 , wherein coupling the first substrate and the second substrate comprises at least one of a fusion bonding process, a wafer bonding process, or a bump bonding process.
13. The method of claim 11 , wherein the plurality of photodetectors comprises a plurality of single photon avalanche photodetectors (SPADs).
14. The method of claim 11 , wherein the bias circuit comprises a passive quenching circuit, wherein the bias voltage is at least 70 volts.
15. The method of claim 11 , wherein the read-out circuit comprises a complementary metal-oxide-semiconductor (CMOS) digital read-out integrated circuit (ROIC) that includes design features less than 32 nanometers in size.