Programmable logic integrated circuit, semiconductor device, and characterization method
An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
1. A programmable logic integrated circuit comprising:
a crossbar switch including a resistance-variable element; and
a logic circuit logically configured with the crossbar switch, wherein
the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch,
the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell, and
circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
2. The programmable logic integrated circuit according to claim 1 , wherein, in the circuit verification, static timing analysis is performed.
3. The programmable logic integrated circuit according to claim 1 , wherein the power supply element includes a buffer.
4. The programmable logic integrated circuit according to claim 1 , wherein the load circuit includes a load resistance and a load capacitance of the resistance-variable element.
5. The programmable logic integrated circuit according to claim 1 , wherein the base leaf cell includes a delay time for the leaf cell to be connected to the power supply element.
6. The programmable logic integrated circuit according to claim 1 , wherein the correction leaf cell includes a correction delay for the leaf cell to be connected to the logic circuit.
7. The programmable logic integrated circuit according to claim 1 , wherein the logic circuit includes a look-up table, and the crossbar switch changes a connection with the look-up table.
8. A semiconductor device comprising the programmable logic integrated circuit according to claim 1 .
9. A programmable logic integrated circuit comprising a plurality of sets of a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein
the programmable logic integrated circuit is divided into a plurality of leaf cells including a power supply element provided between an output line of the crossbar switch and an input line of the crossbar switch on a subsequent stage, and a load circuit including a part of the crossbar switch on a subsequent stage,
the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell, and
circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
10. A characterization method for circuit verification of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, the characterization method comprising:
dividing the programmable logic integrated circuit into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch;
dividing the leaf cell into delay paths each including a base leaf cell and a correction leaf cell; and
integrating a delay time for the base leaf cell and a correction delay for the correction leaf cell into a delay time for the leaf cell.
11. The characterization method according to claim 10 , in which in the circuit verification, static timing analysis is performed.
12. The characterization method according to claim 10 , in which the power supply element includes a buffer.
13. The characterization method according to claim 10 , in which the load circuit includes a load resistance and a load capacitance of the resistance-variable element.
14. The characterization method according to claim 10 , in which the base leaf cell includes a delay time for the leaf cell to be connected to the power supply element.
15. The characterization method according to claim 10 , in which the correction leaf cell includes a correction delay for the leaf cell to be connected to the logic circuit.
16. The characterization method according to claim 10 , in which the logic circuit includes a look-up table, and the crossbar switch changes a connection with the look-up table.