IP Library › Granted Patent US 10,310,049
Granted Patent B2
US 10,310,049 · App. 15/218,006 · Granted Jun 4, 2019

Semiconductor device and failure detection method

Inventors: Yuichi Okuda (Tokyo, JP); Hideo Nakane (Tokyo, JP); Takaya Yamamoto (Tokyo, JP); Keisuke Kimura (Tokyo, JP); Takashi Oshima (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
G01R35/00G01R19/2509H03M1/10H03M1/1038H03M1/1076H03M1/468
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Quick Facts
Patent No.
US 10,310,049
App. No.
15/218,006
Granted
Jun 4, 2019
Kind
B2
Abstract

The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11 ; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11 ; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

Claims (43)

1. A semiconductor device, comprising:

an analog circuit;

a digital assist circuit that corrects an error of a digital signal corresponding to an analog signal processed by the analog circuit; and

a failure detection circuit that detects whether the analog circuit has a failure based on a correction amount by the digital assist circuit, wherein the failure detection circuit detects a failure by evaluating one of:

whether a weight coefficient Eo exceeds a predesignated threshold;

whether a deviation from an average amount of the weight coefficient Eo exceeds a predesignated threshold;

whether a radix (a ratio of weight coefficients of adjacent bits) of an AD converter exceeds a predesignated threshold; and

whether a p-radix (an addition or subtraction of weight coefficients of adjacent bits) of the AD converter exceeds a predesignated threshold.

2. The semiconductor device according to claim 1 , wherein the failure detection circuit determines that the analog circuit has a failure when the correction amount is larger than a predetermined threshold.

3. The semiconductor device according to claim 1 , wherein the failure detection circuit determines that the analog circuit has a failure when a difference between the correction amount and an initial correction amount, which is the correction amount before the analog circuit is used in a normal operation, is larger than a predetermined threshold.

4. The semiconductor device according to claim 3 , further comprising a storage unit that stores the initial correction amount.

5. The semiconductor device according to claim 4 , wherein the storage unit is a programmable nonvolatile memory.

6. The semiconductor device according to claim 3 , wherein the initial correction amount is stored in a storage unit outside of the semiconductor device.

7. The semiconductor device according to claim 1 , wherein:

the analog circuit is an analog-to-digital (AD) converter; and

the digital assist circuit corrects a non-linear error of the digital signal output from the AD converter corresponding to the analog signal input to the AD converter.

8. A semiconductor system comprising:

The semiconductor device according to claim 1 ; and

a higher system that performs predetermined processing for the semiconductor device based on the result of the detection of the failure output from the semiconductor device.

9. A failure detection method, comprising:

correcting an error of a digital signal corresponding to an analog signal processed by an analog circuit using a digital assist circuit; and

detecting whether the analog circuit has a failure based on a correction amount by the digital assist circuit,

wherein the digital assist circuit comprises:

a weight coefficient calculation unit; and

a correction unit.

10. The failure detection method according to claim 9 , wherein it is determined that the analog circuit has a failure when the correction amount is larger than a predetermined threshold.

11. The failure detection method according to claim 9 , wherein it is determined that the analog circuit has a failure when a difference between the correction amount and an initial correction amount, which is the correction amount before the analog circuit is used in a normal operation, is larger than a predetermined threshold.

12. The failure detection method according to claim 11 , further comprising storing the initial correction amount in a storage unit provided on a same semiconductor chip on which the analog circuit is mounted.

13. The failure detection method according to claim 12 , wherein the storage unit is a programmable nonvolatile memory.

14. The failure detection method according to claim 11 , further comprising storing the initial correction amount in a storage unit provided on a semiconductor chip different from a semiconductor chip on which the analog circuit is mounted.

15. The semiconductor device according to claim 7 , wherein the digital assist circuit corrects a non-linear error of the digital signal output by determining and providing a correction amount Eo of a weight coefficient of the AD converter, and

wherein the failure detection circuit detects whether the analog circuit has a failure based on whether the correction amount Eo is larger than a predetermined threshold.

16. The semiconductor device according to claim 7 , wherein a variation of elements constituting the AD converter provides a radix<2.

17. A semiconductor device, comprising:

an analog circuit

a digital assist circuit that corrects an error of a digital signal corresponding to an analog signal processed by the analog circuit; and

a failure detection circuit that detects whether the analog circuit has a failure based on a correction amount by the digital assist circuit,

wherein the analog circuit comprises an analog-to-digital (AD) converter and wherein a variation of elements constituting the AD converter is smaller than 0.5 of a least significant bit (LSB) of the AD converter.

18. The semiconductor device according to claim 1 , wherein the analog circuit comprises one of:

a successive approximation analog-to-digital (AD) converter;

a pipeline type AD converter;

a flash type AD converter; and

an analog circuit in which a correction can be performed by the digital assist circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2016
From: OKUDA, YUICHI; NAKANE, HIDEO; YAMAMOTO, TAKAYA; KIMURA, KEISUKE; OSHIMA, TAKASHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 039247/0505 →
Priority Claims (1)
JP 2015-157914 · Aug 10, 2015 · national
Continuity (1)
Related Publication 20170045578A1 · Feb 16, 2017