Receiver circuit, and semiconductor device and system including the same
A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. The delay circuit may variably delay a data strobe signal based on a delay select signal. The synchronization circuit may generate internal data from data in synchronization with the variably delayed data strobe signal.
1. A receiver circuit comprising:
a first delay circuit configured to delay data, and output delayed data;
a second delay circuit configured to variably delay a data strobe signal based on a delay select signal which is generated based on a rate of data determined from at least one of a column access strobe (CAS) write latency, a write latency and a read latency, and output a delayed data strobe signal; and
a synchronization circuit configured to output the delayed data as internal data in synchronization with the delayed data strobe signal.
2. The receiver circuit according to claim 1 , wherein the first delay circuit comprises:
a first basic delay unit configured to delay the data; and
a second basic delay unit configured to delay an output of the first basic delay unit, and output the delayed data.
3. The receiver circuit according to claim 2 , wherein the second delay circuit comprises:
a variable delay unit configured to variably delay the data strobe signal based on the delay select signal; and
a third basic delay unit configured to delay an output of the variable delay unit, and output the delayed data strobe signal.
4. The receiver circuit according to claim 3 , wherein each of the first to third basic delay units has a fixed delay amount, and the variable delay unit has a delay amount that is variable based on the delay select signal.
5. The receiver circuit according to claim 3 , wherein a delay amount of the second basic delay unit is substantially the same as a delay amount of the third basic delay unit.
6. The receiver circuit according to claim 1 , further comprising:
a data buffer coupled with a data channel and the first delay circuit, and configured to receive the data; and
a data strobe buffer coupled with a strobe channel and the second delay circuit, and configured to receive the data strobe signal.
7. The receiver circuit according to claim 6 ,
wherein the data buffer is coupled with a reference voltage and is configured to receive the data by amplifying the data differentially with the reference voltage; and
wherein the data strobe buffer is coupled with a second strobe channel to receive a complementary data strobe signal, and is configured to receive the data strobe signal by amplifying differentially the data strobe signal and the complementary data strobe signal.
8. The receiver circuit according to claim 1 ,
wherein the synchronization circuit a center of a duration of the delayed data and a rising edge of the delayed data strobe signal are aligned, and
wherein the synchronization circuit samples the delayed data at the rising edge of the delayed data strobe signal.
9. A receiver circuit comprising:
a delay circuit configured to variably delay a data strobe signal based on a delay select signal which is generated based on a rate of data determined from at least one of a column access strobe (CAS) write latency, a write latency and a read latency, and generate a delayed data strobe signal; and
a synchronization circuit configured to output delayed data as internal data in synchronization with the delayed data strobe signal.
10. The receiver circuit according to claim 9 , wherein the delay circuit comprises:
a variable delay unit configured to variably delay the data strobe signal based on the delay select signal; and
a basic delay unit configured to delay an output of the variable delay unit, and generate the delayed data strobe signal.
11. The receiver circuit according to claim 10 , wherein the variable delay unit has a delay amount that is variable depending on the delay select signal, and the basic delay unit has a fixed delay amount.
12. The receiver circuit according to claim 9 , further comprising:
a data buffer coupled with a data channel and the synchronization circuit, and suitable for receiving data and generating the delayed data; and
a data strobe buffer coupled with a strobe channel and the delay circuit, and suitable for receiving the data strobe signal.
13. A receiver circuit comprising:
a data strobe buffer coupled with a strobe channel, and configured to change a receiving time of a data strobe signal based on a delay select signal;
a delay circuit configured to variably delay the data strobe signal based on the delay select signal which is generated based on a rate of data determined from at least one of a column access strobe (CAS) write latency, a write latency and a read latency, and generating a delayed data strobe signal; and
a synchronization circuit configured to output delayed data as internal data in synchronization with the delayed data strobe signal.
14. The receiver circuit according to claim 13 , wherein the delay circuit comprises:
a variable delay unit configured to variably delay the data strobe signal based on the delay select signal; and
a basic delay unit configured to delay an output of the variable delay unit, and generate the delayed data strobe signal.
15. The receiver circuit according to claim 14 , wherein the variable delay unit has a delay amount that is variable depending on the delay select signal, and the basic delay unit has a fixed delay amount.
16. The receiver circuit according to claim 13 , further comprising:
a data buffer coupled with a data channel and the synchronization circuit, and configured to receive data and generating the delayed data.