Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.
1. A method for transferring data from a first semiconductor device to a second semiconductor device, the method comprising:
transferring preamble length information from the second semiconductor device to the first semiconductor device;
storing the preamble length information in a register in the first semiconductor device;
transferring a clock signal from the second semiconductor device to the first semiconductor device;
switching between a Delay Lock Loop (DLL) selection mode in which a DLL circuit is activated and a DLL non-selection mode in which the DLL circuit is not activated;
transferring, from the first semiconductor device to the second semiconductor device, a preamble having a duration specified by the preamble length information followed by a toggle signal having a burst length; and
transferring, from the first semiconductor device to the second semiconductor device, data in synchronization with the toggle signal;
wherein in the DLL selection mode, transferring the toggle signal further comprises:
phase adjusting the toggle signal to the clock signal using the DLL circuit; and
in the DLL non-selection mode, transferring the toggle signal comprises:
transferring the toggle signal with the clock signal as a reference.
2. The method of claim 1 , wherein the register is a mode register.
3. The method of claim 1 , wherein the first semiconductor device is a memory device and the data is read data.
4. The method of claim 1 , wherein the preamble comprises a first logic level for the duration specified by the preamble length information.
5. The method of claim 4 , wherein the first logic level is a low logic level.
6. The method of claim 1 , wherein the first preamble length information is an integer multiple of the period of the clock signal.
7. The method of claim 1 , further comprising transferring a postamble following the toggle signal from the first semiconductor device to the second semiconductor device.
8. The method of claim 1 , wherein in the DLL non-selection mode, the method further comprises:
transferring second preamble length information from the second semiconductor device to the first semiconductor device;
storing the second preamble length information in the register; and
wherein transferring the preamble comprises transferring a preamble having a duration specified by the second preamble length information.
9. The method of claim 8 , wherein the second preamble length information is longer than the first preamble length information.
10. A method for transferring data from a first semiconductor device to a second semiconductor device comprising:
transferring first preamble length information from the second semiconductor device to the first semiconductor device;
storing the first preamble length information in a register in the first semiconductor device;
transferring a clock signal from the second semiconductor device to the first semiconductor device;
transferring a preamble having a duration specified by the first preamble length information, wherein the preamble is followed by a toggle signal having a burst length and the preamble is transferred from the first semiconductor device to the second semiconductor device, wherein the toggle signal is phase adjusted to the clock signal using a Delay Lock Loop (DLL) circuit; and
transferring data in synchronization with the toggle signal from the first semiconductor device to second semiconductor device.