Etch damage and ESL free dual damascene metal interconnect
Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.
1. A semiconductor device manufacturing process, comprising:
providing a substrate;
forming a sacrificial layer over the substrate;
patterning an opening through the sacrificial layer;
filling the opening with conductive material;
removing the sacrificial layer while leaving the conductive material in place;
forming a first dielectric layer along sidewalls of the conductive material left in place; and
prior to forming the sacrificial layer over the substrate, forming a second dielectric layer over the substrate, wherein the sacrificial layer is formed over the second dielectric layer.
2. The process of claim 1 , wherein the conductive material comprises copper.
3. The process of claim 1 , wherein the first dielectric layer is formed by a non-conformal deposition process that leaves air gaps in the first dielectric layer.
4. The process of claim 1 , wherein the opening is aligned over a conductive structure disposed over the substrate, and the conductive material is coupled to the conductive structure.
5. The process of claim 4 , wherein the opening has first sidewalls which are spaced apart by a first distance and the conductive structure has second sidewalls which are spaced apart by a second distance which differs from the first distance.
6. The process of claim 1 , wherein after the removing of the sacrificial layer, the conductive material protrudes above an upper surface of the second dielectric layer, and the first dielectric layer is formed along sidewalls of the protrusion of the conductive material.
7. The process of claim 1 , wherein the first dielectric layer has a porosity greater than 20% and the second dielectric layer has a porosity less than 20%.
8. The process of claim 1 , further comprising:
forming a via opening in the second dielectric prior to forming the sacrificial layer, wherein the forming of the sacrificial layer fills the via opening.
9. The process of claim 8 , wherein the removing of the sacrificial layer re-opens the via opening, and wherein the filling of the opening with the conductive material also fills the via opening with the conductive material.
10. The process of claim 9 , wherein the via opening is filled with the conductive material after the opening has been formed and before the sacrificial layer is removed.
11. A semiconductor device manufacturing process, comprising:
providing a substrate;
forming a sacrificial layer over the substrate;
removing a first selected portion of the sacrificial layer to form an opening in an upper portion of the sacrificial layer;
filling the opening with conductive material to form a conductive feature;
removing a remaining portion of the sacrificial layer while leaving the conductive feature in place;
forming an upper dielectric layer along a sidewall of the conductive feature; and
prior to forming the sacrificial layer over the substrate, forming a lower dielectric layer over the substrate, wherein the sacrificial layer is formed over the lower dielectric layer.
12. The process of claim 11 , wherein after the removing of the remaining portion of the sacrificial layer, at least a portion of the conductive feature protrudes above an upper surface of the lower dielectric layer, and the upper dielectric layer is formed along sidewalls of the at least the portion of the conductive feature.
13. The process of claim 11 , wherein the upper dielectric layer has a porosity greater than 20% and the lower dielectric layer has a porosity less than 20%.
14. A semiconductor device manufacturing process, comprising:
providing a substrate;
forming a first dielectric layer over the substrate;
after the first dielectric layer is formed over the substrate, forming a layer, which comprises polyimide (PI), polypropylene glycol (PPG), polybutadine (PB), polyethylene glycol (PEG), polycaprolactonediol (PCL), or amorphous carbon, over the first dielectric layer;
patterning an opening through the layer;
filling the opening with conductive material;
removing the layer while leaving the conductive material in place; and
forming a second dielectric layer along sidewalls of the conductive material left in place.
15. The process of claim 14 , wherein the opening is a trench opening and the conductive material filling the opening corresponds to a metal line within a back-end-of-line metallization structure.
16. The process of claim 14 , wherein the conductive material comprises copper.
17. The process of claim 14 , wherein the second dielectric layer is formed by a non-conformal deposition process that leaves air gaps in the dielectric layer.
18. The process of claim 14 , wherein the opening is aligned over a conductive structure disposed over the substrate, and the conductive material is coupled to the conductive structure.
19. The process of claim 18 , wherein a bottommost surface of the opening is defined by both an upper surface of the conductive structure and an upper surface of the first dielectric layer.
20. The process of claim 14 , wherein removing the layer while leaving the conductive material in place exposes the first dielectric layer.