IP Library Granted Patent US 10,312,432
Granted Patent B2
US 10,312,432 · App. 15/091,846 · Granted Jun 4, 2019

Magnetic memory device and techniques for forming

Inventors: Tsung-Liang Chen (Hamilton, MA); Shurong Liang (Poughkeepsie, NY); Alexander C. Kontos (Beverly, MA)
Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
H01L43/02H01L43/08H01L43/12
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Quick Facts
Patent No.
US 10,312,432
App. No.
15/091,846
Granted
Jun 4, 2019
Kind
B2
Abstract

A method may include: providing a device stack, the device stack comprising sidewall portions and extending above a substrate base, the device stack further including a plurality of metal layers; depositing an interface layer conformally over the device stack using an atomic layer deposition process, the interface layer comprising a first insulator material; depositing an encapsulation layer on the interface layer, the encapsulation layer comprising a second insulator material; and depositing an interlevel dielectric disposed on the encapsulation layer, the interlevel dielectric comprising a third insulator material.

Claims (21)

1. A method, comprising:

providing a device stack, the device stack comprising sidewall portions and extending above a substrate base, the device stack further including a plurality of metal layers;

depositing an interface layer conformally over the device stack using an atomic layer deposition process, the interface layer comprising a first nitride material;

depositing an encapsulation layer on the interface layer, the encapsulation layer comprising a second nitride material; and

depositing an interlevel dielectric disposed on the encapsulation layer, the interlevel dielectric comprising a third insulator material, wherein the depositing the interface layer comprises selecting a reaction chemistry that prevents formation of halogen-containing radicals, amino groups or reactive oxygen radicals.

2. The method of claim 1 , the first insulator material comprising silicon nitride or Si—C—N.

3. The method of claim 1 , the second insulator material comprising silicon nitride.

4. The method of claim 1 , the interface layer having a thickness of one to ten nanometers.

5. The method of claim 1 , the depositing the interface layer comprising using a plasma enhanced atomic layer deposition process.

6. The method of claim 1 , the depositing the encapsulation layer comprising growing the encapsulation layer using a plasma enhanced chemical vapor deposition process.

7. The method of claim 1 , wherein the device stack comprises a magnetic tunnel junction device having a plurality of magnetic layers and at least one insulator layer.

8. The method of claim 5 , wherein the depositing the interface layer takes place at a temperature of 150° C. to 250° C.

9. The method of claim 1 , wherein the depositing the interface layer takes place at a temperature of 150° C. to 400° C.

10. The method of claim 1 , wherein the depositing the interface layer comprises providing silyl-terminated molecules or alkylaminosilanes molecules.

11. A method of forming a magnetic device, comprising:

providing a device stack, the device stack extending above a substrate base and comprising sidewall portions, the device stack further including a plurality of magnetic layers;

depositing an interface layer conformally over the device stack using an atomic layer deposition process, the interface layer comprising a nitride material having a thickness of one nanometer to three nanometers;

depositing an encapsulation layer on the interface layer, the encapsulation layer comprising silicon nitride; and

depositing an interlevel dielectric disposed on the encapsulation layer, the interlevel dielectric comprising an insulating material, wherein the depositing the interface layer comprises selecting a reaction chemistry that prevents formation of halogen-containing radicals, amino groups or reactive oxygen radicals.

12. The method of claim 11 , wherein the insulator material of the interface layer is a S—C—N mixture.

13. The method of claim 11 , wherein the depositing the interface layer comprises depositing the insulator material while not exposing the device stack to a plasma.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2016
From: CHEN, TSUNG-LIANG; LIANG, SHURONG; KONTOS, ALEXANDER C.
To: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
Reel/Frame 038337/0953 →
Continuity (1)
Related Publication 20170294569A1 · Oct 12, 2017