Optimized image feature extraction
One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.
1. An image processing circuitry comprising:
a feature extraction circuitry to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale; and
an optimization circuitry to optimize an operation of the feature extraction circuitry, each optimization to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry;
wherein:
the feature extraction circuitry comprises an integral image circuitry to determine an integral image of a feature patch associated with the feature point location, a sample point (SP) intensity circuitry to determine a pixel intensity of a square sample point region associated with a sample point, or a combination thereof;
when the feature extraction circuitry comprises said integral image circuitry, said optimization circuitry is to configure the integral image circuitry to determine each integral image value utilizing a register, a line buffer and two addition operations; and
when the feature extraction circuitry comprises said SP intensity circuitry, said optimization circuitry is to configure the SP intensity circuitry to smooth the intensity of the square sample point region using a box filter.
2. The image processing circuitry of claim 1 , wherein the optimization circuitry is to determine whether a spatial locality exists between a plurality of feature points.
3. The image processing circuitry of claim 1 , wherein the feature extraction circuitry comprises said SP intensity circuitry, and said optimization circuitry is to adjust a location of the sample point based, at least in part, on an orientation of a feature patch associated with the feature point location, utilizing an orientation vector.
4. The image processing circuitry of claim 1 , wherein the optimization circuitry is to sort a plurality of pairs of sample points according to an index of a sample point of each pair.
5. The image processing circuitry of claim 1 , wherein the feature extraction circuitry comprises said integral image circuitry, and said optimization circuitry is to configure the integral image circuitry to store a selected integral image value to an image cache.
6. The image processing circuitry of claim 1 , wherein the optimization circuitry is to configure the feature extraction circuitry to determine the feature descriptor utilizing intermediate floating-point precision.
7. A method comprising:
determining, by a feature extraction circuitry, a feature descriptor based, at least in part, on a feature point location and a corresponding scale; and
optimizing, by an optimization circuitry, an operation of the feature extraction circuitry, each optimization to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry;
wherein:
the feature extraction circuitry comprises an integral image circuitry, a sample point (SP) intensity circuitry, or a combination thereof, and the method further comprises:
when the feature extraction circuitry comprises said integral image circuitry, determining, with the integral image circuitry, an integral image of a feature patch associated with the feature point location, and configuring, by the optimization circuitry, the integral image circuitry to determine each integral image value utilizing a register, a line buffer and two addition operations; and
when the feature extraction circuitry comprises said SP intensity circuitry, determining, by said SP intensity circuitry, a pixel intensity of a square sample point region associated with a sample point; and configuring, by the optimization circuitry, the SP intensity circuitry to smooth the intensity of the square sample point region using a box filter.
8. The method of claim 7 , further comprising determining, by the optimization circuitry, whether a spatial locality exists between a plurality of feature points.
9. The method of claim 7 , wherein the feature extraction circuitry comprises said SP intensity circuitry, and the method further comprises further comprising adjusting, by the optimization circuitry, a location of the sample point based, at least in part, on an orientation of a feature patch associated with the feature point location, utilizing an orientation vector.
10. The method of claim 7 , further comprising sorting, by the optimization circuitry, a plurality of pairs of sample points according to an index of a sample point of each pair.
11. The method of claim 7 , wherein the feature extraction circuitry comprises said integral image circuitry, and the method further comprises configuring, by the optimization circuitry, the integral image circuitry to store a selected integral image value to an image cache.
12. The method of claim 7 , further comprising configuring, by the optimization circuitry, the feature extraction circuitry to determine the feature descriptor utilizing intermediate floating-point precision.
13. An image feature system comprising:
a processor circuitry;
a system memory; and
an image processing circuitry comprising:
a feature extraction circuitry to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale; and
an optimization circuitry to optimize an operation of the feature extraction circuitry, each optimization to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry;
wherein:
the feature extraction circuitry comprises an integral image circuitry to determine an integral image of a feature patch associated with the feature point location, a sample point (SP) intensity circuitry to determine a pixel intensity of a square sample point region associated with a sample point, or a combination thereof;
when the feature extraction circuitry comprises said integral image circuitry, determining, with the integral image circuitry, an integral image of a feature patch associated with the feature point location, and configuring, by the optimization circuitry, the integral image circuitry to determine each integral image value utilizing a register, a line buffer and two addition operations;
when the feature extraction circuitry comprises said SP intensity circuitry, determining, by said SP intensity circuitry, a pixel intensity of a square sample point region associated with a sample point; and configuring, by the optimization circuitry, the SP intensity circuitry to smooth the intensity of the square sample point region using a box filter.
14. The image feature system of claim 13 , wherein the optimization circuitry is to determine whether a spatial locality exists between a plurality of feature points.
15. The image feature system of claim 13 , wherein the feature extraction circuitry comprises said SP intensity circuitry, and the optimization circuitry is to adjust a location of the sample point based, at least in part, on an orientation of a feature patch associated with the feature point location, utilizing an orientation vector.
16. The image feature system of claim 13 , wherein the optimization circuitry is to sort a plurality of pairs of sample points according to an index of a sample point of each pair.
17. The image feature system of claim 13 , wherein the feature extraction circuitry comprises said integral image circuitry, and the optimization circuitry is to configure the integral image circuitry to store a selected integral image value to an image cache.
18. The image feature system of claim 13 , wherein the processor circuitry is selected from the group comprising a general purpose processor, a special purpose processor, a graphics processing unit, a digital signal processing unit, a vector processing unit, a microcontroller and a finite state machine microcontroller.
19. The image feature system of claim 13 , wherein the optimization circuitry is to configure the feature extraction circuitry to determine the feature descriptor utilizing intermediate floating-point precision.