IP Library › Granted Patent US 10,319,279
Granted Patent B2
US 10,319,279 · App. 15/438,448 · Granted Jun 11, 2019

Spatial temporal phase shifted polarity aware dither

Inventors: Chaohao Wang (Cupertino, CA); Paolo Sacchetto (Cupertino, CA); Sheng Zhang (Milpitas, CA); Yang Li (Los Angeles, CA); Myung-Je Cho (San Jose, CA); Marc Albrecht (San Francisco, CA)
Assignee: Apple Inc.
G09G3/2055G09G3/2022G09G2320/0247G09G2320/0666
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Quick Facts
Patent No.
US 10,319,279
App. No.
15/438,448
Granted
Jun 11, 2019
Kind
B2
Abstract

This application relates to performing certain dithering processes to eliminate display artifacts such as flicker, which can be caused by charge accumulation at the display. The dither process can be performed by a display controller that uses a group lookup method for identifying groups of dithering patterns that can be combined to expand a number of color values available to the display. The dither process can also be performed as a temporal process that incorporates groups of dithering patterns into frames and shifts a spatial arrangement of the groups of dithering patterns over a sequence of frames. Additionally, the dither process can incorporate counters that count the number of times a particular spatial arrangement of dithering patterns has been used in a sequence of frames in order that each spatial arrangement of dithering patterns will share an average count with other spatial arrangements over a sequence of frames.

Claims (41)

1. A method for operating a display, comprising:

receiving a spatial pattern of color values for a frame in a sequence of frames, each color value of the spatial pattern of color values having most significant bits and least significant bits, and the spatial pattern of color values having a spatial pattern of most significant bits and a spatial pattern of least significant bits;

selecting a phase based on a position of the frame in the sequence of frames;

selecting a dither pattern based on the spatial pattern of least significant bits and the selected phase using a phase lookup table;

tracking a first count of a first phase and a second count of a second phase used within a cycle;

bypassing a dither pattern associated with the first phase when the first count exceeds the second count within the cycle; and

providing output data that combines the spatial pattern of most significant bits and the dither pattern.

2. The method of claim 1 , wherein the dither pattern comprises a spatial pattern of binary values.

3. The method of claim 1 , wherein the dither pattern is stored in a lookup table under a group of dither patterns that have multiple phases, and each dither pattern in the group is associated with an individual phase.

4. The method of claim 3 , wherein the group of dither patterns includes positive polarity frame dither patterns and negative polarity frame dither patterns that are available alternatively in each frame in the sequence of frames.

5. The method of claim 1 , wherein the spatial pattern of color values is associated with a block of pixels, the block of pixels comprises multiple sub-blocks of pixels and the block of pixels is associated with a spatial arrangement of multiple phases, the selecting of the dither pattern for each sub-block of pixels is based on the spatial arrangement of the multiple phases.

6. The method of claim 5 , wherein between an odd frame and an even frame in the sequence of frames, the phases are spatially rearranged by 180 degree; and between the odd frame and a next odd frame in the sequence of frames, the phases are spatially rearranged by 90 degree.

7. The method of claim 5 , wherein the spatial arrangement of multiple phases is determined by a randomization process.

8. A computing device comprising:

a display panel; and

a processor connected to the display panel, the processor configured to compile display output data in accordance with dither patterns that are associated with different phases, the phases are shifted over a sequence of image frames, wherein the display panel is associated with different refresh rates and the processor is further configured to:

track a first count of a first phase is used within a cycle;

track a second count of a second phase is used within the cycle; and

bypass a dither pattern associated with the first phase when the first count exceeds the second count within the cycle.

9. The computing device of claim 8 , wherein the processor is coupled with a memory that stores a lookup table having entries that provide correspondence between combinations of least significant bits and the dither patterns; and

the dither patterns comprises a first group of dither patterns that correspond to positive polarity frames and a second group of dither patterns than correspond to negative polarity frames.

10. The computing device of claim 8 , wherein the shifting of the phases comprises rearranging spatial locations of the phases.

11. The computing device of claim 8 , wherein the shifting of the phases comprises changing phases associated with a group of pixels over time.

12. The computing device of claim 8 , wherein the processor is coupled with a memory that stores a lookup table having entries that provide correspondence between combinations of least significant bits and the dither patterns; and

wherein the shifting of the phases comprises changing a first dither pattern of the dither patterns to a second dither pattern of the dither patterns, the first dither pattern is associated with a higher average luminance than the second dither pattern.

13. The computing device of claim 8 , wherein the display panel further comprises a first group of pixels of a denser color and a second group of pixels of a less dense color; and

the processor is further configured to perform a first spatial dithering horizontally and vertically across the first group of pixels and to perform a second spatial dithering diagonally across the second group of pixels.

14. A system comprising:

a display;

a processor; and

a memory that is configured to store instructions that when executed by the processor, cause the system to perform operations comprising:

receiving an input corresponding to a first block of pixel data for the display;

selecting a block dither pattern according to a spatial pattern of least significant bits in the first block of pixel data, wherein each block dither pattern is associated with a phase, wherein the phase is shifted over the sequence of frames;

tracking a first count of a first phase and a second count of a second phase used within a cycle;

bypassing a block dither pattern associated with the first phase when the first count exceeds the second count within the cycle; and

outputting, to the display, a sequence of second blocks of pixel data for display by the display over a sequence of frames, each second block of pixel data being based on the block dither pattern.

15. The system of claim 14 , wherein the sequence of second blocks of pixel data is associated with a block of 2×2 pixels.

16. The system of claim 14 further comprises a lookup table stored in the memory, the lookup table comprises entries that associate different blocks of pixel data with different groups of dither patterns.

17. The system of claim 14 , wherein the sequence of second blocks of pixel data is associated with a block of 4×4 pixels associated with multiple phases, the block of 4×4 pixels comprising sub-blocks of 2×2 pixels, each sub-block of 2×2 pixels associated with an individual phase, and the phases are shifted spatially over the sequence of frames.

18. The system of claim 14 , wherein the sequence of second blocks of pixel data is associated with a block of pixels comprising multiple sub-blocks, and each sub-block has a spatial arrangement of phases that is determined by a randomization process.

19. The system of claim 14 , wherein the sequence of second blocks of pixel data are associated with a block of pixels that is divided into four quadrants, and four blocks of dither pattern are selected for each second blocks of pixel data, each block of dither pattern is associated with a different phase.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2017
From: WANG, CHAOHAO; SACCHETTO, PAOLO; ZHANG, SHENG; LI, YANG; CHO, MYUNG-JE; ALBRECHT, MARC
To: APPLE INC.
Reel/Frame 041326/0784 →
Continuity (2)
Provisional Application 62349591 · Jun 13, 2016
Related Publication 20170358255A1 · Dec 14, 2017